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Age
Files
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*
Improve "pmux2shiftx"
Clifford Wolf
2019-04-20
2
-11
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+9
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Fix some typos
Clifford Wolf
2019-04-20
1
-2
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+2
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Improvements in "pmux2shiftx"
Clifford Wolf
2019-04-20
2
-13
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+53
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Improvements in pmux2shiftx
Clifford Wolf
2019-04-20
3
-33
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+36
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Add test for pmux2shiftx
Clifford Wolf
2019-04-20
2
-0
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+52
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Improve pmux2shift ctrl permutation finder
Clifford Wolf
2019-04-20
1
-27
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+114
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Complete rewrite of pmux2shiftx
Clifford Wolf
2019-04-20
1
-27
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+265
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Import initial pmux2shiftx from eddieh
Clifford Wolf
2019-04-20
2
-0
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+82
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Improve "show" handling of 0/1/X/Z padding
Clifford Wolf
2019-04-20
1
-2
/
+21
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Change "ne" to "neq" in btor2 output
Clifford Wolf
2019-04-19
1
-1
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+1
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Add tests/aiger/.gitignore
Clifford Wolf
2019-04-19
1
-0
/
+2
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Spelling fixes
Eddie Hung
2019-04-19
1
-2
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+2
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Update to ABC 3709744
Clifford Wolf
2019-04-18
1
-1
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+1
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Merge pull request #917 from YosysHQ/eddie/fix_retime
Eddie Hung
2019-04-18
4
-38
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+46
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Fix abc's remap_name to not ignore [^0-9] when extracting sid
Eddie Hung
2019-04-18
1
-12
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+16
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ABC to call retime all the time
Eddie Hung
2019-04-18
1
-15
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+11
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Revert "synth_* with -retime option now calls abc with -D 1 as well"
Eddie Hung
2019-04-18
11
-15
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+15
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Merge branch 'master' into eddie/fix_retime
Eddie Hung
2019-04-18
7
-75
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+72
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Update to ABC d1b6413
Clifford Wolf
2019-04-17
1
-1
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+1
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Merge pull request #939 from YosysHQ/revert895
Eddie Hung
2019-04-16
1
-28
/
+0
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Revert #895
Eddie Hung
2019-04-16
1
-28
/
+0
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*
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Merge pull request #937 from YosysHQ/revert-932-eddie/fixdlatch
Eddie Hung
2019-04-15
2
-4
/
+3
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Revert "Recognise default entry in case even if all cases covered (fix for #9...
Eddie Hung
2019-04-15
2
-4
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+3
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Merge pull request #936 from YosysHQ/README-fix-quotes
Eddie Hung
2019-04-15
1
-2
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+2
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README: fix some incorrect quoting.
whitequark
2019-04-15
1
-2
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+2
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Merge pull request #928 from litghost/add_xc7_sim_models
Eddie Hung
2019-04-12
3
-41
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+60
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Remove BUFGCTRL, BUFHCE and LUT6_2 from cells_xtra.
Keith Rothman
2019-04-12
3
-52
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+14
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Fix LUT6_2 definition.
Keith Rothman
2019-04-09
1
-3
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+3
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Add additional cells sim models for core 7-series primatives.
Keith Rothman
2019-04-09
1
-0
/
+57
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Merge pull request #933 from dh73/master
Clifford Wolf
2019-04-12
1
-3
/
+9
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Fixing issues in CycloneV cell sim
Diego
2019-04-11
1
-3
/
+9
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Merge pull request #932 from YosysHQ/eddie/fixdlatch
Clifford Wolf
2019-04-12
2
-3
/
+4
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Add default entry to testcase
Eddie Hung
2019-04-11
1
-2
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+3
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Recognise default entry in case even if all cases covered (#931)
Eddie Hung
2019-04-11
1
-1
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+1
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synth_* with -retime option now calls abc with -D 1 as well
Eddie Hung
2019-04-10
11
-15
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+15
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Revert "abc -dff now implies "-D 0" otherwise retiming doesn't happen"
Eddie Hung
2019-04-10
1
-2
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+0
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Revert ""&nf -D 0" fails => use "-D 1" instead"
Eddie Hung
2019-04-10
1
-1
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+1
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Merge remote-tracking branch 'origin/master' into eddie/fix_retime
Eddie Hung
2019-04-10
2
-4
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+5
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Fix a few typos
Eddie Hung
2019-04-08
1
-3
/
+3
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Merge pull request #919 from YosysHQ/multiport_transp
Clifford Wolf
2019-04-08
1
-1
/
+2
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memory_bram: Fix multiport make_transp
David Shah
2019-04-07
1
-1
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+2
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Add retime test
Eddie Hung
2019-04-05
1
-0
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+6
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Fix S0 -> S1
Eddie Hung
2019-04-05
1
-1
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+1
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Move techamp t:$_DFF_?N? to before abc call
Eddie Hung
2019-04-05
1
-2
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+2
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Retry
Eddie Hung
2019-04-05
1
-1
/
+1
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"&nf -D 0" fails => use "-D 1" instead
Eddie Hung
2019-04-05
1
-1
/
+1
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Resolve @daveshah1 comment, update synth_xilinx help
Eddie Hung
2019-04-05
2
-7
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+9
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synth_xilinx to techmap FFs after abc call, otherwise -retime fails
Eddie Hung
2019-04-05
1
-3
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+3
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abc -dff now implies "-D 0" otherwise retiming doesn't happen
Eddie Hung
2019-04-05
1
-0
/
+2
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Add "read_ilang -lib"
Clifford Wolf
2019-04-05
5
-3
/
+39
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