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* Merge pull request #1572 from nakengelhardt/scratchpad_passEddie Hung2019-12-183-0/+136
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| * use extra_argsN. Engelhardt2019-12-181-1/+1
| * add assert option to scratchpad commandN. Engelhardt2019-12-163-19/+49
| * add periods and newlines to help messageN. Engelhardt2019-12-131-5/+5
| * add test and make help message more verboseN. Engelhardt2019-12-122-1/+20
| * add a command to read/modify scratchpad contentsN. Engelhardt2019-12-122-0/+87
* | Merge pull request #1584 from YosysHQ/mwk/xilinx-flaky-testEddie Hung2019-12-181-2/+4
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| * | tests/xilinx: fix flaky mux testMarcin Kościelnicki2019-12-181-2/+4
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* | xilinx: Add xilinx_dffopt pass (#1557)Marcin Kościelnicki2019-12-1811-27/+638
* | xilinx: Improve flip-flop handling.Marcin Kościelnicki2019-12-188-49/+242
* | Send people to symbioticeda.com instead of verific.comClifford Wolf2019-12-182-5/+26
* | Merge pull request #1574 from YosysHQ/eddie/xilinx_lutramEddie Hung2019-12-1613-65/+529
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| * \ Merge branch 'eddie/xilinx_lutram' of github.com:YosysHQ/yosys into eddie/xil...Eddie Hung2019-12-161-2/+8
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| | * | Populate DID/DOD even if unusedEddie Hung2019-12-161-2/+8
| * | | Rename *RAM{32,64}M rules to RAM{32X2,64X1}QEddie Hung2019-12-162-6/+6
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| * | Disable RAM16X1D testEddie Hung2019-12-131-17/+17
| * | Disable RAM16X1D match rule; carry-over from LUT4 archesEddie Hung2019-12-131-6/+9
| * | RAM64M8 to also have [5:0] for addressEddie Hung2019-12-131-8/+8
| * | Remove extraneous synth_xilinx callEddie Hung2019-12-121-2/+0
| * | Add tests for these new modelsEddie Hung2019-12-121-0/+40
| * | Add RAM32X6SDP and RAM64X3SDP modesEddie Hung2019-12-122-8/+120
| * | Fix RAM64M model to have 6 bit address busEddie Hung2019-12-121-4/+4
| * | Add #1460 testcaseEddie Hung2019-12-121-0/+34
| * | Add memory rules for RAM16X1D, RAM32M, RAM64MEddie Hung2019-12-122-0/+168
| * | Rename memory tests to lutram, add more xilinx testsEddie Hung2019-12-129-53/+156
* | | Merge pull request #1521 from dh73/diego/memattrEddie Hung2019-12-167-48/+374
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| * | | Enforce non-existenceEddie Hung2019-12-161-0/+4
| * | | Update docEddie Hung2019-12-161-4/+6
| * | | Add another testEddie Hung2019-12-161-1/+8
| * | | More sloppiness, thanks @dh73 for spottingEddie Hung2019-12-161-4/+4
| * | | Accidentally commented out testsEddie Hung2019-12-161-47/+47
| * | | Add unconditional match blocks for force RAMEddie Hung2019-12-162-4/+45
| * | | OopsEddie Hung2019-12-161-4/+1
| * | | Merge blockram testsEddie Hung2019-12-163-47/+81
| * | | Update xc7/xcu bram rulesEddie Hung2019-12-161-8/+4
| * | | Implement 'attributes' grammarEddie Hung2019-12-161-80/+88
| * | | Merge branch 'diego/memattr' of https://github.com/dh73/yosys into diego/memattrEddie Hung2019-12-164-1/+238
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| * | | Fixing compiler warning/issues. Moving test script to the correct placeDiego H2019-12-162-14/+14
| * | | Removing fixed attribute value to !ramstyle rulesDiego H2019-12-152-3242/+4
| * | | Merging attribute rules into a single match block; Adding testsDiego H2019-12-155-86/+3465
| * | | Refactoring memory attribute matching based on IEEE 1364.1 and Tool specificDiego H2019-12-132-0/+96
* | | | Merge pull request #1575 from rodrigomelo9/masterEddie Hung2019-12-153-4/+4
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| * | | | Fixed some missing "verilog_" in documentationRodrigo Alejandro Melo2019-12-133-4/+4
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* | | | Merge pull request #1577 from gromero/for-yosysEddie Hung2019-12-151-1/+1
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| * | | | manual: Fix text in Abstract sectionGustavo Romero2019-12-111-1/+1
* | | | | Merge pull request #1578 from noopwafel/eqneq-debugEddie Hung2019-12-151-1/+1
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| * | | | Fix opt_expr.eqneq.cmpzero debug printAlyssa Milburn2019-12-151-1/+1
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* | | | Merge pull request #1533 from dh73/bram_xilinxEddie Hung2019-12-133-6/+101
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| * | | Renaming BRAM memory tests for the sake of uniformityDiego H2019-12-132-6/+6
| * | | Fixing citation in xc7_xcu_brams.txt file. Fixing RAMB36E1 test.Diego H2019-12-122-7/+7
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