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| | * | | | synth_xilinx: Initial Spartan 6 block RAM inference support.Marcin Koƛcielnicki2019-07-119-8/+598
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| * | | | Merge pull request #1185 from koriakin/xc-ff-init-valsEddie Hung2019-07-112-6/+6
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| | * | | | xilinx: Fix the default values for FDPE/FDSE INIT attributes to match ISE/Viv...Marcin Koƛcielnicki2019-07-112-6/+6
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| * / / / Enable &mfs for abc9, even if it only currently works for ice40Eddie Hung2019-07-111-1/+1
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| * | | Merge pull request #1172 from whitequark/write_verilog-Sa-as-qmarkClifford Wolf2019-07-111-2/+8
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| | * | | write_verilog: write RTLIL::Sa aka - as Verilog ?.whitequark2019-07-091-2/+8
| * | | | Merge pull request #1179 from whitequark/attrmap-procClifford Wolf2019-07-111-0/+19
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| | * | | | attrmap: also consider process, switch and case attributes.whitequark2019-07-101-0/+19
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* | | | | Add Tsu offset to boxes, and commentsEddie Hung2019-07-111-6/+11
* | | | | ABC doesn't like negative delays in flop boxes...Eddie Hung2019-07-111-6/+6
* | | | | Fix FDCE_1 boxEddie Hung2019-07-111-1/+1
* | | | | Revert "$pastQ should be first input"Eddie Hung2019-07-111-13/+13
* | | | | Propagate INIT attrEddie Hung2019-07-111-5/+5
* | | | | $pastQ should be first inputEddie Hung2019-07-111-13/+13
* | | | | Fix typoEddie Hung2019-07-111-1/+1
* | | | | Short out async boxEddie Hung2019-07-111-0/+14
* | | | | Simplify to $__ABC_ASYNC boxEddie Hung2019-07-112-19/+8
* | | | | $__ABC_FD_ASYNC_MUX.Q -> YEddie Hung2019-07-111-1/+1
* | | | | Missing debug messageEddie Hung2019-07-111-0/+1
* | | | | Error out if abc9 not called with -lut or -lutsEddie Hung2019-07-111-0/+3
* | | | | Count $_NOT_ cells turned into $lutsEddie Hung2019-07-111-7/+2
* | | | | WIP for fixing partitioning, temporarily do not partitionEddie Hung2019-07-111-12/+34
* | | | | Restore from masterEddie Hung2019-07-101-0/+1
* | | | | Another typoEddie Hung2019-07-101-1/+1
* | | | | abc_flop to also get topologically sortedEddie Hung2019-07-101-11/+10
* | | | | write_verilog with *.v extensionEddie Hung2019-07-101-1/+1
* | | | | Fix clk_pol for FD*_1Eddie Hung2019-07-102-4/+3
* | | | | Another typoEddie Hung2019-07-101-1/+1
* | | | | Another typoEddie Hung2019-07-101-1/+1
* | | | | Fix spacingEddie Hung2019-07-101-1/+1
* | | | | Use \$currQEddie Hung2019-07-101-4/+9
* | | | | Remove -retime from abc9, revert to abc behav with separate clock/en domainsEddie Hung2019-07-101-29/+61
* | | | | Preserve all parameters, plus some extra ones for clk/en polarityEddie Hung2019-07-101-10/+66
* | | | | Small optEddie Hung2019-07-101-2/+1
* | | | | Change how to specify flops to ABC againEddie Hung2019-07-103-33/+63
* | | | | Use split_tokens()Eddie Hung2019-07-102-25/+19
* | | | | Remove params from FD*_1 variantsEddie Hung2019-07-101-12/+3
* | | | | Fix typo, and have !{PRE,CLR} behave as CEEddie Hung2019-07-101-14/+14
* | | | | Move ABC FF stuff to abc_ff.v; add support for other FD* typesEddie Hung2019-07-104-27/+135
* | | | | Uncomment IS_C_INVERTED parameterEddie Hung2019-07-101-1/+1
* | | | | synth_xilinx's map_cells stage to techmap ff_map.vEddie Hung2019-07-101-0/+2
* | | | | Fix box numberingEddie Hung2019-07-102-5/+5
* | | | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-07-1039-246/+999
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| * | | | Merge pull request #1180 from YosysHQ/eddie/no_abc9_retimeEddie Hung2019-07-103-6/+15
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| | * | | | Error out if -abc9 and -retime specifiedEddie Hung2019-07-103-6/+15
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| * | | | Merge pull request #1148 from YosysHQ/xc7muxEddie Hung2019-07-107-49/+415
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| | * | | | Add some spacingEddie Hung2019-07-101-9/+9
| | * | | | Add some ASCII art explaining mux decompositionEddie Hung2019-07-101-0/+21
| | * | | | Call muxpack and pmux2shiftx before cmp2lutEddie Hung2019-07-091-9/+12
| | * | | | Restore opt_clean back to original placeEddie Hung2019-07-091-2/+1