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* abc9 needs a clean afterwardsEddie Hung2019-12-161-2/+4
* Put $__ABC9_{FF_,ASYNC} into same clock domain as abc9_flopEddie Hung2019-12-161-5/+27
* Use sigmap signalEddie Hung2019-12-161-1/+1
* Skip $inout transformation if not a PIEddie Hung2019-12-161-3/+5
* Revert "write_xaiger: use sigmap bits more consistently"Eddie Hung2019-12-161-4/+5
* write_xaiger: use sigmap bits more consistentlyEddie Hung2019-12-161-5/+4
* Name inputs/outputs of aiger 'i%d' and 'o%d'Eddie Hung2019-12-131-13/+6
* Remove 'clkpart' entry in CHANGELOGEddie Hung2019-12-121-1/+0
* Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-12-1218-64/+238
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| * abc9_map.v: fix Xilinx LUTRAMEddie Hung2019-12-121-6/+6
| * Update README.md :: abc_ -> abc9_Eddie Hung2019-12-111-3/+3
| * Fix bitwidth mismatch; suppresses iverilog warningEddie Hung2019-12-111-4/+4
| * Merge pull request #1564 from ZirconiumX/intel_housekeepingDavid Shah2019-12-118-6/+6
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| | * synth_intel: a10gx -> arria10gxDan Ravensloft2019-12-105-4/+4
| | * synth_intel: cyclone10 -> cyclone10lpDan Ravensloft2019-12-105-4/+4
| * | Merge pull request #1545 from YosysHQ/eddie/ice40_wrapcarry_attrEddie Hung2019-12-098-51/+225
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| | * | ice40_opt to restore attributes/name when unwrappingEddie Hung2019-12-091-0/+15
| | * | ice40_wrapcarry -unwrap to preserve 'src' attributeEddie Hung2019-12-091-1/+9
| | * | unmap $__ICE40_CARRY_WRAPPER in testEddie Hung2019-12-091-1/+21
| | * | -unwrap to create $lut not SB_LUT4 for opt_lutEddie Hung2019-12-091-7/+5
| | * | Sensitive to direct inst of $__ICE40_CARRY_WRAPPER; recreate SB_LUT4Eddie Hung2019-12-092-8/+12
| | * | ice40_wrapcarry to really preserve attributes via -unwrap optionEddie Hung2019-12-094-39/+61
| | * | Drop keep=0 attributes on SB_CARRYEddie Hung2019-12-062-2/+10
| | * | Merge SB_CARRY+SB_LUT4's attributes when creating $__ICE40_CARRY_WRAPPEREddie Hung2019-12-051-0/+1
| | * | Add WIP test for unwrapping $__ICE40_CARRY_WRAPPEREddie Hung2019-12-051-0/+30
| | * | Check SB_CARRY name also preservedEddie Hung2019-12-031-0/+1
| | * | $__ICE40_CARRY_WRAPPER to use _TECHMAP_REPLACE_ for SB_CARRY to preserveEddie Hung2019-12-031-1/+1
| | * | ice40_opt to ignore (* keep *) -ed cellsEddie Hung2019-12-031-0/+5
| | * | ice40_wrapcarry to preserve SB_CARRY's attributesEddie Hung2019-12-031-0/+2
| | * | Add testcaseEddie Hung2019-12-031-0/+60
* | | | abc9_map.v: fix Xilinx LUTRAMEddie Hung2019-12-121-6/+6
* | | | Fix commentEddie Hung2019-12-091-1/+1
* | | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-12-0619-971/+1773
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| * | | Merge pull request #1555 from antmicro/fix-macc-xilinx-testEddie Hung2019-12-061-1/+1
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| | * | | tests: arch: xilinx: Change order of arguments in macc.shJan Kowalewski2019-12-061-1/+1
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| * | | Merge pull request #1551 from whitequark/manual-cell-operandsClifford Wolf2019-12-053-43/+82
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| | * | kernel: require \B_SIGNED=0 on $shl, $sshl, $shr, $sshr.whitequark2019-12-042-8/+26
| | * | manual: document behavior of many comb cells more precisely.whitequark2019-12-041-35/+56
| * | | xilinx: Add tristate buffer mapping. (#1528)Marcin Kościelnicki2019-12-042-9/+16
| * | | iopadmap: Refactor and fix tristate buffer mapping. (#1527)Marcin Kościelnicki2019-12-042-146/+196
| * | | xilinx: Add models for LUTRAM cells. (#1537)Marcin Kościelnicki2019-12-043-624/+831
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| * | Merge pull request #1524 from pepijndevos/gowindffinitClifford Wolf2019-12-035-114/+571
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| | * | update testPepijn de Vos2019-12-031-2/+3
| | * | Use -match-init to not synth contradicting init valuesPepijn de Vos2019-12-032-11/+13
| | * | attempt to fix formattingPepijn de Vos2019-11-252-292/+292
| | * | gowin: add and test dff init valuesPepijn de Vos2019-11-254-41/+495
| * | | Merge pull request #1542 from YosysHQ/dave/abc9-loop-fixDavid Shah2019-12-022-29/+46
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| | * | | abc9: Fix breaking of SCCsDavid Shah2019-12-012-29/+46
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| * | | Merge pull request #1539 from YosysHQ/mwk/ilang-bounds-checkClifford Wolf2019-12-011-0/+4
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| | * | read_ilang: do bounds checking on bit indicesMarcin Kościelnicki2019-11-271-0/+4
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