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| | * | | | | | | | | | | | Use pool<> not std::set<> for determinismEddie Hung2019-12-011-4/+4
| | * | | | | | | | | | | | clkpart -unpart into 'finalize'Eddie Hung2019-11-281-3/+4
| | * | | | | | | | | | | | Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dffEddie Hung2019-11-281-1/+1
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| | | * | | | | | | | | | | | Move \init signal for non-port signals as long as internally drivenEddie Hung2019-11-281-1/+1
| | * | | | | | | | | | | | | Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dffEddie Hung2019-11-271-0/+31
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| | | * | | | | | | | | | | | Fix multiple driver issueEddie Hung2019-11-271-2/+7
| | | * | | | | | | | | | | | Add multiple driver testcaseEddie Hung2019-11-271-0/+31
| | * | | | | | | | | | | | | Fix multiple driver issueEddie Hung2019-11-271-2/+7
| | * | | | | | | | | | | | | Add comment, use sigmapEddie Hung2019-11-271-2/+2
| | * | | | | | | | | | | | | Revert "Fold loop"Eddie Hung2019-11-271-3/+6
| | * | | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-11-275-7/+100
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| | * | | | | | | | | | | | | | ean call after abc{,9}Eddie Hung2019-11-271-1/+2
| | * | | | | | | | | | | | | | Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dffEddie Hung2019-11-271-7/+3
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| | | * | | | | | | | | | | | | Do not replace constants with same wireEddie Hung2019-11-271-7/+3
| | * | | | | | | | | | | | | | Merge remote-tracking branch 'origin/eddie/write_xaiger_improve' into xaig_dffEddie Hung2019-11-274-34/+30
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| | * \ \ \ \ \ \ \ \ \ \ \ \ \ \ Merge remote-tracking branch 'origin/eddie/clkpart' into xaig_dffEddie Hung2019-11-270-0/+0
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| | | * | | | | | | | | | | | | | | clkpart to analyse async flops tooEddie Hung2019-11-251-0/+8
| | * | | | | | | | | | | | | | | | Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dffEddie Hung2019-11-272-49/+94
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| | | * | | | | | | | | | | | | | | CleanupEddie Hung2019-11-271-5/+3
| | | * | | | | | | | | | | | | | | Check for nullptrEddie Hung2019-11-271-1/+1
| | | * | | | | | | | | | | | | | | Stray log_dumpEddie Hung2019-11-271-1/+0
| | | * | | | | | | | | | | | | | | Revert "submod to bitty rather bussy, for bussy wires used as input and output"Eddie Hung2019-11-272-42/+76
| | | * | | | | | | | | | | | | | | Promote output wires in sigmap so that can be detectedEddie Hung2019-11-261-8/+4
| | | * | | | | | | | | | | | | | | Fix wire widthEddie Hung2019-11-261-2/+2
| | | * | | | | | | | | | | | | | | Fix submod -hiddenEddie Hung2019-11-261-5/+6
| | | * | | | | | | | | | | | | | | Add -hidden option to submodEddie Hung2019-11-261-11/+25
| | | * | | | | | | | | | | | | | | Update docs with bullet pointsEddie Hung2019-11-261-10/+9
| | | * | | | | | | | | | | | | | | Move \init from source wire to submod if output portEddie Hung2019-11-251-0/+7
| | | * | | | | | | | | | | | | | | Add testcase where \init is copiedEddie Hung2019-11-251-0/+18
| | * | | | | | | | | | | | | | | | Merge branch 'master' into xaig_dffEddie Hung2019-11-260-0/+0
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| | | * \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ Merge branch 'master' of github.com:YosysHQ/yosysEddie Hung2019-11-22312-25148/+44916
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| | | * | | | | | | | | | | | | | | | | Fix typoEddie Hung2019-09-271-1/+1
| | * | | | | | | | | | | | | | | | | | xaiger: do not promote output wiresEddie Hung2019-11-261-5/+0
| | * | | | | | | | | | | | | | | | | | Move 'clean' from map_luts to finalizeEddie Hung2019-11-261-1/+1
| | * | | | | | | | | | | | | | | | | | Fix submod -hiddenEddie Hung2019-11-261-5/+6
| | * | | | | | | | | | | | | | | | | | clkpart to use 'submod -hidden'Eddie Hung2019-11-261-1/+1
| | * | | | | | | | | | | | | | | | | | Add -hidden option to submodEddie Hung2019-11-261-20/+40
| | * | | | | | | | | | | | | | | | | | Fold loopEddie Hung2019-11-251-6/+3
| | * | | | | | | | | | | | | | | | | | Do not sigmap keep bits inside write_xaigerEddie Hung2019-11-251-1/+1
| | * | | | | | | | | | | | | | | | | | Fix debugEddie Hung2019-11-251-3/+3
| | * | | | | | | | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-11-2510-18/+83
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| | * | | | | | | | | | | | | | | | | | | Special abc9_clock wire to contain only clock signalEddie Hung2019-11-251-12/+10
| | * | | | | | | | | | | | | | | | | | | abc9 to contain time callEddie Hung2019-11-251-1/+1
| | * | | | | | | | | | | | | | | | | | | abc9 to no longer to clock partitioning, operate on whole modules onlyEddie Hung2019-11-251-139/+32
| | * | | | | | | | | | | | | | | | | | | clkpart to analyse async flops tooEddie Hung2019-11-251-0/+8
| | * | | | | | | | | | | | | | | | | | | Merge remote-tracking branch 'origin/eddie/clkpart' into xaig_dffEddie Hung2019-11-231-2/+3
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| | | * | | | | | | | | | | | | | | | | | More oopsiesEddie Hung2019-11-231-2/+3
| | * | | | | | | | | | | | | | | | | | | Conditioning abc9 on POs not accurate due to cellsEddie Hung2019-11-231-15/+6
| | * | | | | | | | | | | | | | | | | | | For abc9, run clkpart before ff_map and after abc9Eddie Hung2019-11-231-0/+2
| | * | | | | | | | | | | | | | | | | | | Merge remote-tracking branch 'origin/eddie/clkpart' into xaig_dffEddie Hung2019-11-231-13/+27
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