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* Avoid parameter values with size 0 ($mem cells)Clifford Wolf2015-04-053-11/+16
* make all vector-size related integer params in $mem sim model signedClifford Wolf2015-04-051-6/+6
* Added $_MUX4_, $_MUX8_, and $_MUX16_ cell typesClifford Wolf2015-04-054-2/+131
* Added "dffinit", Support for initialized Xilinx DFFClifford Wolf2015-04-046-8/+132
* Added "init" attribute support to verilog backendClifford Wolf2015-04-041-0/+5
* appnote 012 fixClifford Wolf2015-04-041-2/+2
* Appnote 012Clifford Wolf2015-04-042-115/+115
* Updated ABC to 51705b168d7aClifford Wolf2015-04-041-2/+2
* Merge pull request #55 from ahmedirfan1983/masterClifford Wolf2015-04-044-27/+492
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| * Update READMEAhmed Irfan2015-04-031-1/+1
| * Delete btor.ysAhmed Irfan2015-04-031-18/+0
| * Update READMEAhmed Irfan2015-04-031-1/+1
| * separated memory next from write cellAhmed Irfan2015-04-031-7/+55
| * Merge branch 'master' of https://github.com/cliffordwolf/yosysAhmed Irfan2015-04-03266-4671/+18443
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* | documentation improvementsClifford Wolf2015-03-292-1/+5
* | Ignore celldefine directive in verilog front-endClifford Wolf2015-03-251-0/+3
* | Fixes in cmos_cells.vClifford Wolf2015-03-251-3/+12
* | Fixed detection of absolute paths in ABC for win32Clifford Wolf2015-03-223-3/+13
* | Added blif reference to appnote 010Clifford Wolf2015-03-221-1/+5
* | Merge branch 'master' of github.com:cliffordwolf/yosysClifford Wolf2015-03-201-2/+2
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| * | Fixed handling of quotes in liberty parserClifford Wolf2015-03-181-2/+2
* | | fix for python 2.6.6Clifford Wolf2015-03-203-165/+172
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* | Added hierarchy -auto-topClifford Wolf2015-03-181-1/+33
* | Added Verilog backend $dffsr supportClifford Wolf2015-03-181-1/+51
* | Documentation for JSON format, added attributesClifford Wolf2015-03-061-16/+156
* | Added very first version of "synth_ice40"Clifford Wolf2015-03-054-0/+211
* | Fixed bug in "hierarchy" for parametric designsClifford Wolf2015-03-041-20/+19
* | Json bugfixClifford Wolf2015-03-031-1/+1
* | Json backend improvementsClifford Wolf2015-03-031-4/+12
* | Added write_blif -attrClifford Wolf2015-03-021-18/+33
* | Added JSON backendClifford Wolf2015-03-022-0/+262
* | Const-fold parameter defs on-demand in AstNode::detectSignWidthWorker()Clifford Wolf2015-03-011-2/+4
* | Added $assume support to write_smt2Clifford Wolf2015-02-261-4/+19
* | Added non-std verilog assume() statementClifford Wolf2015-02-2610-25/+67
* | Added $assume cell typeClifford Wolf2015-02-265-2/+57
* | Merge branch 'master' of github.com:cliffordwolf/yosysClifford Wolf2015-02-252-14/+54
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| * | Added "keep_hierarchy" attributeClifford Wolf2015-02-252-14/+54
* | | Bugfix in iopadmapClifford Wolf2015-02-251-10/+3
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* | Some cleanups in "clean"Clifford Wolf2015-02-243-7/+26
* | Fixed compilation problems with gcc 4.6.3; use enum instead of const ints.Clifford Wolf2015-02-241-2/+4
* | Minor "write_smt2" help msg changeClifford Wolf2015-02-221-1/+1
* | Fixed "check -assert"Clifford Wolf2015-02-221-1/+1
* | Added "<mod>_a" and "<mod>_i" to write_smt2 outputClifford Wolf2015-02-221-23/+149
* | Added "check -assert" docClifford Wolf2015-02-221-0/+3
* | Added "check -assert"Clifford Wolf2015-02-221-0/+8
* | Fixed "sat -initsteps" off-by-one bugClifford Wolf2015-02-221-1/+1
* | Added "sat -stepsize" and "sat -tempinduct-step"Clifford Wolf2015-02-211-21/+64
* | sat docu changeClifford Wolf2015-02-211-0/+3
* | When "sat -tempinduct-baseonly -maxsteps N" reaches maxsteps it is a good thing.Clifford Wolf2015-02-211-0/+5
* | Added "sat -tempinduct-baseonly -tempinduct-inductonly"Clifford Wolf2015-02-211-66/+92
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