aboutsummaryrefslogtreecommitdiffstats
Commit message (Expand)AuthorAgeFilesLines
...
* | | | Add support for signed $shift/$shiftx in smt2 back-endClifford Wolf2018-11-011-1/+3
* | | | Merge branch 'igloo2'Clifford Wolf2018-10-315-0/+377
|\ \ \ \
| * | | | Fix sf2 LUT interfaceClifford Wolf2018-10-312-12/+12
| * | | | Basic SmartFusion2 and IGLOO2 synthesis supportClifford Wolf2018-10-315-0/+377
| |/ / /
* | | | Merge pull request #680 from jburgess777/fix-empty-string-back-assertClifford Wolf2018-10-301-1/+1
|\ \ \ \ | |/ / / |/| | |
| * | | Avoid assert when label is an empty stringJon Burgess2018-10-281-1/+1
|/ / /
* | | Merge pull request #678 from whentze/masterClifford Wolf2018-10-251-2/+2
|\ \ \
| * | | fix unhandled std::out_of_range when calling yosys with 3-character argumentwhentze2018-10-221-2/+2
| | |/ | |/|
* | | Fix minor typo in error messageClifford Wolf2018-10-251-1/+1
* | | Merge pull request #679 from udif/pr_syntax_errorClifford Wolf2018-10-2514-14/+78
|\ \ \
| * | | Rename the generic "Syntax error" message from the Verilog/SystemVerilog pars...Udi Finkelstein2018-10-2514-14/+78
* | | | Merge pull request #677 from daveshah1/ecp5_dspClifford Wolf2018-10-233-1/+97
|\ \ \ \ | |_|/ / |/| | |
| * | | ecp5: Remove DSP parameters that don't workDavid Shah2018-10-221-21/+0
| * | | ecp5: Add DSP blackboxesDavid Shah2018-10-213-1/+118
| |/ /
* | | Improve read_verilog range out of bounds warningClifford Wolf2018-10-201-6/+6
* | | Merge pull request #674 from rubund/feature/svinterface_at_topClifford Wolf2018-10-2011-70/+599
|\ \ \ | |/ / |/| |
| * | Refactor code to avoid code duplication + added commentsRuben Undheim2018-10-204-136/+113
| * | Support for SystemVerilog interfaces as a port in the top level module + test...Ruben Undheim2018-10-209-10/+561
| * | Fixed memory leakRuben Undheim2018-10-201-0/+1
|/ /
* | Merge pull request #673 from daveshah1/ecp5_improveClifford Wolf2018-10-194-6/+17
|\ \
| * | ecp5: Sim model fixesDavid Shah2018-10-191-3/+5
| * | ecp5: Add latch inferenceDavid Shah2018-10-193-3/+12
|/ /
* | Merge pull request #672 from daveshah1/fix_bramClifford Wolf2018-10-191-0/+1
|\ \
| * | memory_bram: Reset make_outreg when growing read portsDavid Shah2018-10-191-0/+1
* | | Merge pull request #671 from rafaeltp/masterClifford Wolf2018-10-191-2/+3
|\ \ \ | | |/ | |/|
| * | adding offset info to memoriesrafaeltp2018-10-181-1/+1
| * | adding offset info to memoriesrafaeltp2018-10-181-2/+3
* | | Merge pull request #670 from rubund/feature/basic_svinterface_testClifford Wolf2018-10-196-9/+248
|\ \ \ | |/ / |/| |
| * | Basic test for checking correct synthesis of SystemVerilog interfacesRuben Undheim2018-10-186-9/+248
|/ /
* | Update ABC to git rev 14d985aClifford Wolf2018-10-181-1/+1
* | Merge pull request #659 from rubund/sv_interfacesClifford Wolf2018-10-1811-21/+649
|\ \
| * | Handle FIXME for modport members without type directly in frontRuben Undheim2018-10-131-6/+8
| * | Documentation improvements etc.Ruben Undheim2018-10-135-38/+77
| * | Fix build error with clangRuben Undheim2018-10-121-1/+1
| * | Support for 'modports' for System Verilog interfacesRuben Undheim2018-10-128-14/+121
| * | Synthesis support for SystemVerilog interfacesRuben Undheim2018-10-1210-21/+501
* | | Merge pull request #657 from mithro/xilinx-vprClifford Wolf2018-10-181-3/+2
|\ \ \
| * | | xilinx: Still map LUT7/LUT8 to Xilinx specific primitives.Tim 'mithro' Ansell2018-10-081-3/+2
| |/ /
* | | Merge pull request #664 from tklam/ignore-verilog-protectClifford Wolf2018-10-181-0/+3
|\ \ \
| * | | ignore protect endprotectargama2018-10-161-0/+3
| |/ /
* | | Update ABC to git rev c5b48bbClifford Wolf2018-10-171-1/+1
* | | Minor code cleanups in liberty front-endClifford Wolf2018-10-171-16/+5
* | | Merge pull request #660 from tklam/parse-liberty-detect-ff-latchClifford Wolf2018-10-171-0/+17
|\ \ \
| * | | detect ff/latch before processing other nodesargama2018-10-141-0/+17
| |/ /
* | | Merge pull request #663 from aman-goel/masterClifford Wolf2018-10-171-32/+51
|\ \ \
| * | | Minor updateAman Goel2018-10-152-3/+3
| * | | Update to .smv backendAman Goel2018-10-012-35/+54
| * | | Merge pull request #4 from YosysHQ/masterAman Goel2018-10-0131-107/+529
| |\ \ \
* | \ \ \ Merge pull request #658 from daveshah1/ecp5_bramClifford Wolf2018-10-179-20/+371
|\ \ \ \ \
| * | | | | ecp5: Disable LSR inversionDavid Shah2018-10-162-21/+21
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-07 08:55:08 +0000