| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | Added some svgviewer code for possible future switch to QGraphicsWebView | Clifford Wolf | 2013-11-27 | 3 | -6/+20 |
| * | Merge branch 'master' of github.com:cliffordwolf/yosys | Clifford Wolf | 2013-11-27 | 1 | -1/+1 |
| |\ |
|
| | * | Set version number to 0.1.0+ | Clifford Wolf | 2013-11-27 | 1 | -1/+1 |
| * | | Tighter integration of ABC build | Clifford Wolf | 2013-11-27 | 4 | -7/+35 |
| |/ |
|
| * | Started implementing undef support in "sat" command | Clifford Wolf | 2013-11-25 | 1 | -12/+103 |
| * | Bugfixes in new "stat" command | Clifford Wolf | 2013-11-25 | 1 | -7/+1 |
| * | Added "stat" command | Clifford Wolf | 2013-11-25 | 2 | -0/+219 |
| * | Improvements in satgen undef handling | Clifford Wolf | 2013-11-25 | 2 | -87/+209 |
| * | Improvements in satgen undef handling | Clifford Wolf | 2013-11-25 | 2 | -31/+142 |
| * | Added ezsat vec_const() api | Clifford Wolf | 2013-11-25 | 2 | -17/+26 |
| * | Started implementing undef handling in satgen | Clifford Wolf | 2013-11-25 | 2 | -34/+202 |
| * | Removed undef feature from ezsat api | Clifford Wolf | 2013-11-25 | 2 | -11/+2 |
| * | Using simplemap mappers from techmap | Clifford Wolf | 2013-11-24 | 3 | -742/+104 |
| * | Added simplemap pass | Clifford Wolf | 2013-11-24 | 2 | -0/+518 |
| * | Renamed stdcells_sim.v to simcells.v and fixed blackbox.v | Clifford Wolf | 2013-11-24 | 6 | -22/+25 |
| * | Added module->avail_parameters (for advanced techmap features) | Clifford Wolf | 2013-11-24 | 3 | -3/+14 |
| * | Added techmap -D and -I options | Clifford Wolf | 2013-11-24 | 1 | -2/+16 |
| * | Added verilog frontend -ignore_redef option | Clifford Wolf | 2013-11-24 | 3 | -5/+19 |
| * | Added "techmap -share_map" option | Clifford Wolf | 2013-11-24 | 2 | -4/+13 |
| * | Early wire/reg/parameter width calculation in ast/simplify | Clifford Wolf | 2013-11-24 | 1 | -0/+5 |
| * | Updated TODOs | Clifford Wolf | 2013-11-24 | 1 | -2/+1 |
| * | Fixed xilinx/example_sim_counter test bench | Clifford Wolf | 2013-11-24 | 1 | -1/+1 |
| * | Added proper dumping of signed/unsigned parameters to verilog backend | Clifford Wolf | 2013-11-24 | 1 | -4/+6 |
| * | Added support for signed parameters in ilang | Clifford Wolf | 2013-11-24 | 3 | -2/+9 |
| * | Removed now obsolete test cases | Clifford Wolf | 2013-11-24 | 3 | -72/+0 |
| * | Remove auto_wire framework (smarter than the verilog standard) | Clifford Wolf | 2013-11-24 | 9 | -126/+5 |
| * | Implemented correct handling of signed module parameters | Clifford Wolf | 2013-11-24 | 8 | -8/+19 |
| * | Added modelsim support to autotest | Clifford Wolf | 2013-11-24 | 3 | -8/+37 |
| * | Fixed "flatten" top-module detection: Only use on fully selected designs | Clifford Wolf | 2013-11-24 | 1 | -3/+4 |
| * | Fixed "make install" dependencies | Clifford Wolf | 2013-11-24 | 1 | -1/+1 |
| * | Added "top" attribute to mark top module in hierarchy | Clifford Wolf | 2013-11-24 | 6 | -3/+63 |
| * | Updated command-reference-manual.tex | Clifford Wolf | 2013-11-23 | 1 | -10/+26 |
| * | AppNote 010 typo fixes and corrections | Clifford Wolf | 2013-11-23 | 1 | -55/+60 |
| * | AppNote 010 progress | Clifford Wolf | 2013-11-23 | 4 | -75/+230 |
| * | Improved handling of techmap special wires | Clifford Wolf | 2013-11-23 | 1 | -1/+3 |
| * | Improved handling of initialized registers | Clifford Wolf | 2013-11-23 | 1 | -10/+10 |
| * | Added more generic _TECHMAP_ wire mechanism to techmap pass | Clifford Wolf | 2013-11-23 | 3 | -78/+192 |
| * | Making prograss on Appnote 010 | Clifford Wolf | 2013-11-23 | 2 | -8/+93 |
| * | Progress on AppNote 010 | Clifford Wolf | 2013-11-22 | 1 | -6/+63 |
| * | Started to write on AppNote 010: Verilog to BLIF | Clifford Wolf | 2013-11-22 | 2 | -0/+178 |
| * | Updated command-reference-manual.tex | Clifford Wolf | 2013-11-22 | 1 | -8/+192 |
| * | Renamed "placeholder" to "blackbox" | Clifford Wolf | 2013-11-22 | 12 | -27/+27 |
| * | Some driver changes/fixes | Clifford Wolf | 2013-11-22 | 1 | -5/+5 |
| * | Fixed O(n^2) performance bug in verilog preprocessor | Clifford Wolf | 2013-11-22 | 1 | -1/+1 |
| * | Added more performance measurement infrastructure | Clifford Wolf | 2013-11-22 | 2 | -2/+43 |
| * | Enable {* .. *} feature per default (removes dependency to REJECT feature in ... | Clifford Wolf | 2013-11-22 | 5 | -24/+3 |
| * | Massive performance improvement from refactoring RTLIL::SigSpec::optimize() | Clifford Wolf | 2013-11-22 | 1 | -30/+13 |
| * | Added SigBit struct and refactored RTLIL::SigSpec::extract | Clifford Wolf | 2013-11-22 | 2 | -24/+119 |
| * | Improved make rules for profiling and debugging | Clifford Wolf | 2013-11-22 | 1 | -3/+3 |
| * | Updated abc | Clifford Wolf | 2013-11-21 | 4 | -11/+39 |
