| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| * | | | | | | | | Improve "show" handling of 0/1/X/Z padding | Clifford Wolf | 2019-04-20 | 1 | -2/+21 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | | | | | | | Change "ne" to "neq" in btor2 output | Clifford Wolf | 2019-04-19 | 1 | -1/+1 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | we need to do this because they changed the parser: https://github.com/Boolector/btor2tools/commit/e97fc9cedabadeec4f621de22096e514f862c690 Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | | | | | | | Add tests/aiger/.gitignore | Clifford Wolf | 2019-04-19 | 1 | -0/+2 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | | | | | | | Spelling fixes | Eddie Hung | 2019-04-19 | 1 | -2/+2 | |
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| * | | | | | | | | Update to ABC 3709744 | Clifford Wolf | 2019-04-18 | 1 | -1/+1 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | | | | | | | Merge pull request #917 from YosysHQ/eddie/fix_retime | Eddie Hung | 2019-04-18 | 4 | -38/+46 | |
| |\ \ \ \ \ \ \ \ | |/ / / / / / / |/| | | | | | | | Retime by default when abc -dff | |||||
| | * | | | | | | | Fix abc's remap_name to not ignore [^0-9] when extracting sid | Eddie Hung | 2019-04-18 | 1 | -12/+16 | |
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| | * | | | | | | | ABC to call retime all the time | Eddie Hung | 2019-04-18 | 1 | -15/+11 | |
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| | * | | | | | | | Revert "synth_* with -retime option now calls abc with -D 1 as well" | Eddie Hung | 2019-04-18 | 11 | -15/+15 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 9a6da9a79a22e984ee3eec02caa230b66f10e11a. | |||||
| | * | | | | | | | Merge branch 'master' into eddie/fix_retime | Eddie Hung | 2019-04-18 | 7 | -75/+72 | |
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| * | | | | | | | | Update to ABC d1b6413 | Clifford Wolf | 2019-04-17 | 1 | -1/+1 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | | | | | | | Merge pull request #939 from YosysHQ/revert895 | Eddie Hung | 2019-04-16 | 1 | -28/+0 | |
| |\ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | Revert #895 (mux-to-shiftx optimisation) | |||||
| | * | | | | | | | | Revert #895 | Eddie Hung | 2019-04-16 | 1 | -28/+0 | |
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| * | | | | | | | | Merge pull request #937 from YosysHQ/revert-932-eddie/fixdlatch | Eddie Hung | 2019-04-15 | 2 | -4/+3 | |
| |\ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | Revert "Recognise default entry in case even if all cases covered (fix for #931)" | |||||
| | * | | | | | | | | Revert "Recognise default entry in case even if all cases covered (fix for ↵ | Eddie Hung | 2019-04-15 | 2 | -4/+3 | |
| |/ / / / / / / / | | | | | | | | | | | | | | | | | | | | | | | | | #931)" | |||||
| * | | | | | | | | Merge pull request #936 from YosysHQ/README-fix-quotes | Eddie Hung | 2019-04-15 | 1 | -2/+2 | |
| |\ \ \ \ \ \ \ \ | |_|_|_|_|/ / / |/| | | | | | | | README: fix some incorrect quoting | |||||
| | * | | | | | | | README: fix some incorrect quoting. | whitequark | 2019-04-15 | 1 | -2/+2 | |
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| * | | | | | | | Merge pull request #928 from litghost/add_xc7_sim_models | Eddie Hung | 2019-04-12 | 3 | -41/+60 | |
| |\ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | Add additional cells sim models for core 7-series primitives. | |||||
| | * | | | | | | | Remove BUFGCTRL, BUFHCE and LUT6_2 from cells_xtra. | Keith Rothman | 2019-04-12 | 3 | -52/+14 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> | |||||
| | * | | | | | | | Fix LUT6_2 definition. | Keith Rothman | 2019-04-09 | 1 | -3/+3 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> | |||||
| | * | | | | | | | Add additional cells sim models for core 7-series primatives. | Keith Rothman | 2019-04-09 | 1 | -0/+57 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> | |||||
| * | | | | | | | | Merge pull request #933 from dh73/master | Clifford Wolf | 2019-04-12 | 1 | -3/+9 | |
| |\ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | Fixing issues in CycloneV cell sim | |||||
| | * | | | | | | | | Fixing issues in CycloneV cell sim | Diego | 2019-04-11 | 1 | -3/+9 | |
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| * | | | | | | | | Merge pull request #932 from YosysHQ/eddie/fixdlatch | Clifford Wolf | 2019-04-12 | 2 | -3/+4 | |
| |\ \ \ \ \ \ \ \ | |/ / / / / / / |/| | | | | | | | Recognise default entry in case even if all cases covered (fix for #931) | |||||
| | * | | | | | | | Add default entry to testcase | Eddie Hung | 2019-04-11 | 1 | -2/+3 | |
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| | * | | | | | | | Recognise default entry in case even if all cases covered (#931) | Eddie Hung | 2019-04-11 | 1 | -1/+1 | |
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| | * | | | | | | synth_* with -retime option now calls abc with -D 1 as well | Eddie Hung | 2019-04-10 | 11 | -15/+15 | |
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| | * | | | | | | Revert "abc -dff now implies "-D 0" otherwise retiming doesn't happen" | Eddie Hung | 2019-04-10 | 1 | -2/+0 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 19271bd996a79cb4be1db658fcf18227ee0a1dff. | |||||
| | * | | | | | | Revert ""&nf -D 0" fails => use "-D 1" instead" | Eddie Hung | 2019-04-10 | 1 | -1/+1 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 3c253818cab2013dc4db55732d3e21cfa0dc3f19. | |||||
| | * | | | | | | Merge remote-tracking branch 'origin/master' into eddie/fix_retime | Eddie Hung | 2019-04-10 | 2 | -4/+5 | |
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| * | | | | | | | Fix a few typos | Eddie Hung | 2019-04-08 | 1 | -3/+3 | |
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| * | | | | | | | Merge pull request #919 from YosysHQ/multiport_transp | Clifford Wolf | 2019-04-08 | 1 | -1/+2 | |
| |\ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | memory_bram: Fix multiport make_transp | |||||
| | * | | | | | | | memory_bram: Fix multiport make_transp | David Shah | 2019-04-07 | 1 | -1/+2 | |
| |/ / / / / / / | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
| | * | | | | | | Add retime test | Eddie Hung | 2019-04-05 | 1 | -0/+6 | |
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| | * | | | | | | Fix S0 -> S1 | Eddie Hung | 2019-04-05 | 1 | -1/+1 | |
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| | * | | | | | | Move techamp t:$_DFF_?N? to before abc call | Eddie Hung | 2019-04-05 | 1 | -2/+2 | |
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| | * | | | | | | Retry | Eddie Hung | 2019-04-05 | 1 | -1/+1 | |
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| | * | | | | | | "&nf -D 0" fails => use "-D 1" instead | Eddie Hung | 2019-04-05 | 1 | -1/+1 | |
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| | * | | | | | | Resolve @daveshah1 comment, update synth_xilinx help | Eddie Hung | 2019-04-05 | 2 | -7/+9 | |
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| | * | | | | | | synth_xilinx to techmap FFs after abc call, otherwise -retime fails | Eddie Hung | 2019-04-05 | 1 | -3/+3 | |
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| | * | | | | | | abc -dff now implies "-D 0" otherwise retiming doesn't happen | Eddie Hung | 2019-04-05 | 1 | -0/+2 | |
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| * | | | | | | Add "read_ilang -lib" | Clifford Wolf | 2019-04-05 | 5 | -3/+39 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | | | | | Added missing argument checking to "mutate" command | Clifford Wolf | 2019-04-04 | 1 | -0/+32 | |
| | |_|/ / / |/| | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | | | | Merge pull request #913 from smunaut/fix_proc_mux | Eddie Hung | 2019-04-03 | 1 | -1/+1 | |
| |\ \ \ \ \ | | | | | | | | | | | | | proc_mux: Fix crash when trying to optimize non-existant mux to shiftx | |||||
| | * | | | | | proc_mux: Fix crash when trying to optimize non-existant mux to shiftx | Sylvain Munaut | 2019-04-03 | 1 | -1/+1 | |
| |/ / / / / | | | | | | | | | | | | | | | | | | | | | | | | | | last_mux_cell can be NULL ... Signed-off-by: Sylvain Munaut <tnt@246tNt.com> | |||||
| * | | | | | Merge pull request #912 from YosysHQ/bram_addr_en | Clifford Wolf | 2019-04-03 | 1 | -0/+2 | |
| |\ \ \ \ \ | | | | | | | | | | | | | memory_bram: Consider read enable for address expansion register | |||||
| | * | | | | | memory_bram: Consider read enable for address expansion register | David Shah | 2019-04-02 | 1 | -0/+2 | |
| | | |/ / / | |/| | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
| * | | | | | Merge pull request #910 from ucb-bar/memupdates | Clifford Wolf | 2019-04-03 | 1 | -30/+173 | |
| |\ \ \ \ \ | |/ / / / |/| | | | | Refine memory support to deal with general Verilog memory definitions. | |||||
| | * | | | | Refine memory support to deal with general Verilog memory definitions. | Jim Lawson | 2019-04-01 | 1 | -30/+173 | |
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| * | | | | Merge pull request #895 from YosysHQ/pmux2shiftx | Eddie Hung | 2019-04-02 | 1 | -0/+28 | |
| |\ \ \ \ | |/ / / |/| | | | RFC: Add a pmux-to-shiftx optimisation to proc_mux | |||||
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