aboutsummaryrefslogtreecommitdiffstats
Commit message (Collapse)AuthorAgeFilesLines
* Merge pull request #1319 from TeaEngineering/shuckc/brew-tcl-tkEddie Hung2019-08-221-0/+1
|\ | | | | require tcl-tk in Brewfile
| * require tcl-tk in BrewfileChris Shucksmith2019-08-221-0/+1
| |
* | Merge pull request #1317 from YosysHQ/eddie/opt_expr_shiftxEddie Hung2019-08-222-4/+96
|\ \ | | | | | | opt_expr to trim A port of $shiftx/$shift
| * | Copy-paste typoEddie Hung2019-08-221-1/+1
| | |
| * | Respect opt_expr -keepdc as per @cliffordwolfEddie Hung2019-08-222-1/+15
| | |
| * | Handle $shift and Y_WIDTH > 1 as per @cliffordwolfEddie Hung2019-08-222-5/+51
| | |
| * | Add cover()Eddie Hung2019-08-221-0/+1
| | |
| * | Canonical formEddie Hung2019-08-221-5/+5
| | |
| * | Add testEddie Hung2019-08-211-0/+14
| | |
| * | opt_expr to trim A port of $shiftx if Y_WIDTH == 1Eddie Hung2019-08-211-0/+17
| | |
* | | Bump year in copyright noticeClifford Wolf2019-08-223-3/+3
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | Fix missing newline at end of fileClifford Wolf2019-08-221-1/+1
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | Merge pull request #1289 from mmicko/anlogic_fixesClifford Wolf2019-08-225-91/+162
|\ \ \ | | | | | | | | Anlogic fixes and optimization
| * \ \ Merge remote-tracking branch 'upstream/master' into anlogic_fixesMiodrag Milanovic2019-08-18109-3621/+4745
| |\ \ \
| * | | | Proper arith for Anlogic and use standard passMiodrag Milanovic2019-08-125-91/+162
| | | | |
* | | | | Fix missing newline at end of fileClifford Wolf2019-08-221-1/+1
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | | Merge pull request #1281 from mmicko/efinixClifford Wolf2019-08-229-0/+798
|\ \ \ \ \ | |_|_|_|/ |/| | | | Initial support for Efinix Trion series FPGAs
| * | | | Fix formatingMiodrag Milanovic2019-08-111-2/+2
| | | | |
| * | | | one bit enable signalMiodrag Milanovic2019-08-111-1/+1
| | | | |
| * | | | fix mixing signals on FF mappingMiodrag Milanovic2019-08-111-4/+4
| | | | |
| * | | | Replaced custom step with setundefMiodrag Milanovic2019-08-113-91/+1
| | | | |
| * | | | Fixed data widthMiodrag Milanovic2019-08-111-2/+2
| | | | |
| * | | | Adding new pass to fix carry chainMiodrag Milanovic2019-08-113-0/+124
| | | | |
| * | | | cleanupMiodrag Milanovic2019-08-111-4/+7
| | | | |
| * | | | Fix COMiodrag Milanovic2019-08-091-26/+24
| | | | |
| * | | | Merge remote-tracking branch 'upstream/master' into efinixMiodrag Milanovic2019-08-0958-598/+1321
| |\ \ \ \
| * | | | | clock for ram trough gbufMiodrag Milanovic2019-08-041-0/+6
| | | | | |
| * | | | | Added bram supportMiodrag Milanovic2019-08-046-1/+260
| | | | | |
| * | | | | Custom step to add global clock buffersMiodrag Milanovic2019-08-034-1/+129
| | | | | |
| * | | | | Initial EFINIX supportMiodrag Milanovic2019-08-035-0/+370
| | | | | |
* | | | | | Merge pull request #1316 from YosysHQ/eddie/fix_mem2regClifford Wolf2019-08-222-0/+17
|\ \ \ \ \ \ | | | | | | | | | | | | | | mem2reg to preserve user attributes and src
| * | | | | | mem2reg to preserve user attributes and srcEddie Hung2019-08-212-0/+17
| | |_|_|_|/ | |/| | | |
* | | | | | Merge pull request #1315 from mmicko/fix_dependencieswhitequark2019-08-211-1/+1
|\ \ \ \ \ \ | |/ / / / / |/| | | | | Fix test_pmgen deps
| * | | | | Fix test_pmgen depsMiodrag Milanovic2019-08-211-1/+1
|/ / / / /
* | | | | Merge pull request #1314 from YosysHQ/eddie/fix_techmapClifford Wolf2019-08-214-4/+21
|\ \ \ \ \ | | | | | | | | | | | | techmap -max_iter to apply to each module individually
| * | | | | GrammarEddie Hung2019-08-201-1/+1
| | | | | |
| * | | | | Add testEddie Hung2019-08-203-0/+15
| | | | | |
| * | | | | techmap -max_iter to apply to each module individuallyEddie Hung2019-08-201-4/+6
| | | | | |
* | | | | | Missing newlineEddie Hung2019-08-201-1/+1
| | | | | |
* | | | | | Fix copy-paste typoEddie Hung2019-08-201-1/+1
|/ / / / /
* | | | | Merge pull request #1209 from YosysHQ/eddie/synth_xilinxEddie Hung2019-08-205-16/+23
|\ \ \ \ \ | | | | | | | | | | | | [WIP] synth xilinx renaming, as per #1184
| * \ \ \ \ Merge remote-tracking branch 'origin/master' into eddie/synth_xilinxEddie Hung2019-08-20191-4502/+7003
| |\ \ \ \ \
| * | | | | | Bump abc to fix &mfs bugEddie Hung2019-07-251-1/+1
| | | | | | |
| * | | | | | Update changelogEddie Hung2019-07-221-3/+4
| | | | | | |
| * | | | | | Update Makefile tooEddie Hung2019-07-181-2/+2
| | | | | | |
| * | | | | | Add CHANGELOG entryEddie Hung2019-07-181-0/+3
| | | | | | |
| * | | | | | Work in progress for renaming labels/options in synth_xilinxEddie Hung2019-07-183-14/+17
| | | | | | |
* | | | | | | Merge pull request #1304 from YosysHQ/eddie/abc9_refactorEddie Hung2019-08-206-104/+138
|\ \ \ \ \ \ \ | | | | | | | | | | | | | | | | Refactor abc9 to use port attributes, not module attributes
| * | | | | | | Clarify with 'only'Eddie Hung2019-08-191-1/+1
| | | | | | | |
| * | | | | | | Update docEddie Hung2019-08-191-3/+4
| | | | | | | |
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-22 08:33:19 +0000