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* add tristate buffer and testPepijn de Vos2019-10-283-2/+21
* do not use wide luts in testcasePepijn de Vos2019-10-281-3/+3
* actually run the gowin testsPepijn de Vos2019-10-281-0/+1
* More formattingPepijn de Vos2019-10-281-55/+49
* really really fix formatting maybePepijn de Vos2019-10-281-41/+41
* undo formatting fuckupPepijn de Vos2019-10-281-25/+25
* add wide lutsPepijn de Vos2019-10-283-36/+119
* add 32-bit BRAM and byte-enablesPepijn de Vos2019-10-282-4/+25
* ALU sim tweaksPepijn de Vos2019-10-242-13/+13
* Add some testsPepijn de Vos2019-10-2110-0/+224
* add a few more missing dffPepijn de Vos2019-10-211-7/+16
* add negedge DFFPepijn de Vos2019-10-212-15/+139
* use ADDSUB ALU mode to remove invertersPepijn de Vos2019-10-212-7/+77
* Merge branch 'master' of https://github.com/YosysHQ/yosys into gowinPepijn de Vos2019-10-21275-2678/+32872
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| * ecp5: Pass -nomfs to abc9David Shah2019-10-201-2/+2
| * Merge pull request #1457 from xobs/python-binary-nameMiodrag Milanović2019-10-196-9/+9
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| | * Makefile: don't assume python is called `python3`Sean Cross2019-10-196-9/+9
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| * Merge pull request #1454 from YosysHQ/mmicko/common_testsMiodrag Milanović2019-10-18166-1763/+455
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| | * fixed errorMiodrag Milanovic2019-10-181-1/+1
| | * Unify verilog styleMiodrag Milanovic2019-10-1811-191/+157
| | * Common memory test now sharedMiodrag Milanovic2019-10-1810-89/+5
| | * Remove not needed testsMiodrag Milanovic2019-10-184-52/+0
| | * Share common testsMiodrag Milanovic2019-10-18103-1316/+178
| | * fix yosys pathMiodrag Milanovic2019-10-181-2/+2
| | * Fix path to yosysMiodrag Milanovic2019-10-185-5/+5
| | * Moved all tests in arch sub directoryMiodrag Milanovic2019-10-18151-5/+5
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| * Add async2syncMiodrag Milanovic2019-10-182-8/+8
| * Merge pull request #1435 from YosysHQ/mmicko/efinixMiodrag Milanović2019-10-1827-1/+572
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| | * Merge branch 'master' into mmicko/efinixMiodrag Milanović2019-10-18156-896/+3156
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| * | Merge pull request #1434 from YosysHQ/mmicko/anlogicMiodrag Milanović2019-10-1821-0/+430
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| | * \ Merge branch 'master' into mmicko/anlogicMiodrag Milanović2019-10-18136-896/+2726
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| * | | Merge pull request #1421 from YosysHQ/eddie/pr1352Miodrag Milanović2019-10-1833-0/+669
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| | * \ \ Merge branch 'master' into eddie/pr1352Miodrag Milanović2019-10-18119-987/+2470
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| * | | | Merge pull request #1420 from YosysHQ/eddie/pr1363Miodrag Milanović2019-10-1829-47/+544
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| | * | | | hierarchy - proc reorderMiodrag Milanovic2019-10-1810-17/+21
| | * | | | Make equivalence work with latest masterMiodrag Milanovic2019-10-173-8/+8
| | * | | | remove not needed top moduleMiodrag Milanovic2019-10-172-20/+2
| | * | | | remove not needed top moduleMiodrag Milanovic2019-10-172-17/+2
| | * | | | split muxes synth per typeMiodrag Milanovic2019-10-172-39/+39
| | * | | | Test dffs separetelyMiodrag Milanovic2019-10-172-26/+19
| | * | | | Split latches into separete testsMiodrag Milanovic2019-10-172-42/+27
| | * | | | Fix formattingMiodrag Milanovic2019-10-171-1/+8
| | * | | | Clean verilog code from not used define blockMiodrag Milanovic2019-10-172-12/+0
| | * | | | Removed alu and div_mod test as agreed, ignore generated filesMiodrag Milanovic2019-10-175-70/+1
| | * | | | Test per flip-flop typeMiodrag Milanovic2019-10-172-47/+37
| | * | | | Add -assertEddie Hung2019-10-171-1/+1
| | * | | | Use built-in async2sync call as per #1417Eddie Hung2019-10-171-4/+0
| | * | | | Update mul test to DSP48E1Eddie Hung2019-10-171-9/+2
| | * | | | Update area for div_modEddie Hung2019-10-171-6/+6
| | * | | | Add comment for lack of tristate logic pointing to #1225Eddie Hung2019-10-171-1/+1
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