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| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | write_xaiger back to working with whole modules onlyEddie Hung2019-11-221-5/+2
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dffEddie Hung2019-11-222-1/+44
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| | | * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Cleanup spacingEddie Hung2019-11-221-2/+1
| | | * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | sigmap(wire) should inherit port_output status of POsEddie Hung2019-11-221-1/+19
| | | * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add testcaseEddie Hung2019-11-221-0/+26
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| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Merge branch 'eddie/clkpart' into xaig_dffEddie Hung2019-11-222-1/+2
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| | | * | | | | | | | | | | | | | | | | | | | | | | | | | | | | BracketsEddie Hung2019-11-221-1/+1
| | | * | | | | | | | | | | | | | | | | | | | | | | | | | | | | Entry in Makefile.incEddie Hung2019-11-221-0/+1
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Merge branch 'eddie/clkpart' into xaig_dffEddie Hung2019-11-2215-23/+591
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| | | * | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add to CHANGELOGEddie Hung2019-11-221-0/+1
| | | * | | | | | | | | | | | | | | | | | | | | | | | | | | | | New 'clkpart' to {,un}partition design according to clock/enableEddie Hung2019-11-221-0/+268
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| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | | Revert "write_xaiger to not use module POs but only write outputs if driven"Eddie Hung2019-11-221-23/+11
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | | Missing endmoduleEddie Hung2019-11-221-0/+1
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | | write_xaiger to not use module POs but only write outputs if drivenEddie Hung2019-11-211-11/+23
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | | When expanding upwards, do not capture $__ABC9_{FF,ASYNC}_Eddie Hung2019-11-211-1/+1
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | | Merge branch 'eddie/xaig_dff_adff' into xaig_dffEddie Hung2019-11-215-16/+55
| | |\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | | | | |_|/ / / / / / / / / / / / / / / / / / / / / / / / / / | | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | |
| | | * | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a equiv test tooEddie Hung2019-11-192-0/+23
| | | * | | | | | | | | | | | | | | | | | | | | | | | | | | | Add two testsEddie Hung2019-11-191-0/+12
| | | * | | | | | | | | | | | | | | | | | | | | | | | | | | | abc9 to support async flops $_DFF_[NP][NP][01]_Eddie Hung2019-11-191-1/+2
| | | * | | | | | | | | | | | | | | | | | | | | | | | | | | | Do not drop async control signals in abc_map.vEddie Hung2019-11-191-12/+16
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add testEddie Hung2019-11-211-1/+6
| | | |_|/ / / / / / / / / / / / / / / / / / / / / / / / / / | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | Consistent log message, ignore 's' extensionEddie Hung2019-11-201-2/+3
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | endomain -> ctrldomainEddie Hung2019-11-201-3/+3
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | Add blackbox model for $__ABC9_FF_ so that clock partitioning worksEddie Hung2019-11-201-0/+3
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | Add multi clock testEddie Hung2019-11-201-0/+5
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix INIT valuesEddie Hung2019-11-201-4/+4
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| | * | | | | | | | | | | | | | | | | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-11-19228-24028/+35109
| | |\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | | | | |_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|/ / | | | |/| | | | | | | | | | | | | | | | | | | | | | | | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-10-0814-138/+539
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| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | CleanupEddie Hung2019-10-071-7/+2
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | Rename $currQ to $abc9_currQEddie Hung2019-10-072-54/+54
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | Use "abc9_period" attribute for delay targetEddie Hung2019-10-071-3/+24
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | Get rid of latch_* in write_xaigerEddie Hung2019-10-071-7/+1
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | Update comments in abc9_map.vEddie Hung2019-10-071-131/+57
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove -D_ABC9Eddie Hung2019-10-071-2/+0
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove "write_xaiger -zinit"Eddie Hung2019-10-071-16/+6
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | Add comment on default flop initEddie Hung2019-10-071-0/+1
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | Get rid of output_port lookupEddie Hung2019-10-071-14/+8
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | Do not require changes to cells_sim.v; try and work out comb modelEddie Hung2019-10-056-308/+276
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | Error if $currQ not foundEddie Hung2019-10-051-0/+4
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | abc -> abc9Eddie Hung2019-10-041-3/+3
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix from mergeEddie Hung2019-10-041-1/+1
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-10-048-184/+33
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| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use read_args for read_verilogEddie Hung2019-10-041-3/+6
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix merge issuesEddie Hung2019-10-046-21/+14
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | | Merge remote-tracking branch 'origin/eddie/abc_to_abc9' into xaig_dffEddie Hung2019-10-0434-361/+376
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| | * \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-10-0320-86/+374
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| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | EnglishEddie Hung2019-10-031-3/+3
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | More fixesEddie Hung2019-10-011-16/+16
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Escape Verilog identifiers for legality outside of YosysEddie Hung2019-10-011-48/+48
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | No need to punch ports at allEddie Hung2019-09-302-13/+24
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-22 18:17:39 +0000