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* VCD reader support by using external toolMiodrag Milanovic2022-02-283-0/+21
* Merge pull request #3216 from YosysHQ/claire/simstuffMiodrag Milanović2022-02-282-42/+64
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| * Support extended aiw formatMiodrag Milanovic2022-02-271-23/+44
| * Fix for last clock edge dataMiodrag Milanovic2022-02-252-3/+2
| * Experimental sim changesClaire Xenia Wolf2022-02-251-20/+22
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* Bump versiongithub-actions[bot]2022-02-251-1/+1
* gowin: Remove unnecessary attributesYRabbit2022-02-241-5/+0
* gowin: Add support for true differential outputYRabbit2022-02-241-0/+11
* Merge pull request #3211 from YosysHQ/micko/witnessClaire Xen2022-02-222-2/+97
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| * Fix cycle 0 in aiger witness co-simulationClaire Xenia Wolf2022-02-181-12/+15
| * Changed error messageMiodrag Milanovic2022-02-181-1/+1
| * Added AIGER witness file co simulationMiodrag Milanovic2022-02-181-1/+93
* | Merge pull request #3197 from YosysHQ/claire/smtbmcfixClaire Xen2022-02-221-1/+4
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| * | Add a bit of flexibilty re trace length when processing aiger witnesses in sm...Claire Xenia Wolf2022-02-111-1/+4
* | | Bump versiongithub-actions[bot]2022-02-221-1/+1
* | | Merge pull request #3203 from YosysHQ/micko/sim_ffMiodrag Milanović2022-02-2145-172/+1170
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| * | | Fix handling of ce_over_srstMiodrag Milanovic2022-02-211-3/+2
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| * | simplify logic of handling flip-flops and latchesMiodrag Milanovic2022-02-181-118/+42
| * | Review cleanupMiodrag Milanovic2022-02-171-6/+5
| * | test dlatchsr and adlatchMiodrag Milanovic2022-02-164-4/+94
| * | Added test casesMiodrag Milanovic2022-02-1639-0/+897
| * | Add support for various ff/latch cells simulationMiodrag Milanovic2022-02-163-169/+258
* | | ecp5: Do not use specify in generate in cells_sim.v.Marcelina Kościelnicka2022-02-211-28/+15
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* | Bump versiongithub-actions[bot]2022-02-161-1/+1
* | Merge pull request #3204 from YosysHQ/claire/update-abcMiodrag Milanović2022-02-151-1/+1
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| * | Bump ABC versionMiodrag Milanovic2022-02-151-1/+1
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* | Bump versiongithub-actions[bot]2022-02-151-1/+1
* | verilog: support for time scale delay valuesZachary Snow2022-02-144-4/+42
* | Fix access to whole sub-structs (#3086)Kamil Rakoczy2022-02-147-11/+72
* | Bump versiongithub-actions[bot]2022-02-131-1/+1
* | gowin: Add remaining block RAM blackboxes.Marcelina Kościelnicka2022-02-121-72/+527
* | Bump versiongithub-actions[bot]2022-02-121-1/+1
* | verilog: fix dynamic dynamic range asgn elabZachary Snow2022-02-114-17/+144
* | verilog: fix const func eval with upto variablesZachary Snow2022-02-115-3/+99
* | Merge pull request #2376 from nmoroze/clk2ff-better-namesClaire Xen2022-02-113-9/+40
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| * Merge branch 'master' into clk2ff-better-namesClaire Xen2022-02-11757-8621/+49373
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| * | clk2fflogic: nice names for autogenerated signalsNoah Moroze2021-03-023-9/+39
* | | Merge pull request #3164 from zachjs/fix-ast-warnMiodrag Milanović2022-02-111-1/+1
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| * | fix dumpAst() compilation warningZachary Snow2022-01-181-1/+1
* | | Merge pull request #2019 from boqwxp/gliftClaire Xen2022-02-1121-1/+7849
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| * | | glift: Use ID() rather than string literals.Alberto Gonzalez2020-07-011-11/+11
| * | | glift: Use worker pattern.Alberto Gonzalez2020-07-011-80/+75
| * | | glift: Add support for $_NAND_ and $_NOR_ cells.Alberto Gonzalez2020-07-011-8/+11
| * | | glift: Add support for $_MUX_ and $_NMUX_ cells.Alberto Gonzalez2020-07-011-1/+34
| * | | glift: Add support for $_XOR_ and $_XNOR_ cells.Alberto Gonzalez2020-07-011-15/+79
| * | | glift: Add initial hierarchy support.Alberto Gonzalez2020-07-011-12/+59
| * | | glift: Replace `YS_OVERRIDE` with `override`.Alberto Gonzalez2020-07-011-2/+2
| * | | glift: Add CODEOWNERS entry.Alberto Gonzalez2020-07-011-0/+1
| * | | glift: Add `-simple-cost-model` optionAlberto Gonzalez2020-07-011-20/+45
| * | | glift: Use `qbfsat -O2` instead of manually calling `abc`.Alberto Gonzalez2020-07-018-40/+8
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