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Fixes #2447.
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This adds one simple piece of functionality to opt_expr: when a cell
port is connected to a fully-constant signal (as determined by sigmap),
the port is reconnected directly to the constant value. This is just
enough optimization to fix the "non-constant $meminit input" problem
without requiring a full opt_clean or a separate pass.
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No functional change, but pulls more logic out of the expand_module
function.
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cxxrtl: treat wires with multiple defs as not inlinable
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Fixes #2883.
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cxxrtl: treat assignable internal wires used only for debug as locals
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This issue was introduced in commit 4aa65f40 while fixing #2739.
Fixes #2882.
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cxxrtl: escape colon in variable names in VCD writer
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The following VCD file crashes GTKWave's VCD loader:
$var wire 1 ! x:1 $end
$enddefinitions $end
In practice, a colon can be a part of a variable name that is
translated from a Verilog function, something like:
update$func$.../hdl/hazard3_csr.v:350$2534.$result
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cxxrtl: add debug_item::{get,set}
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Fixes #2877.
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cxxrtl: treat internal wires used only for debug as constants
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Fixes #2739 (again).
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This doesn't do anything useful yet: the patch just adds support for
the syntax to the lexer and parser and adds some tests to check the
syntax parses properly. This generates AST nodes, but doesn't yet
generate RTLIL.
Since our existing hierarchical_identifier parser doesn't allow bit
selects (so you can't do something like foo[1].bar[2].baz), I've also
not added support for a trailing bit select (the "constant_bit_select"
non-terminal in "bind_target_instance" in the spec). If we turn out to
need this in future, we'll want to augment hierarchical_identifier and
its other users too.
Note that you can't easily use the BNF from the spec:
bind_directive ::=
"bind" bind_target_scope [ : bind_target_instance_list]
bind_instantiation ;
| "bind" bind_target_instance bind_instantiation ;
even if you fix the lookahead problem, because code like this matches
both branches in the BNF:
bind a b b_i (.*);
The problem is that 'a' could either be a module name or a degenerate
hierarchical reference. This seems to be a genuine syntactic
ambiguity, which the spec resolves (p739) by saying that we have to
wait until resolution time (the hierarchy pass) and take whatever is
defined, treating 'a' as an instance name if it names both an instance
and a module.
To keep the parser simple, it currently accepts this invalid syntax:
bind a.b : c d e (.*);
This is invalid because we're in the first branch of the BNF above, so
the "a.b" term should match bind_target_scope: a module or interface
identifier, not an arbitrary hierarchical identifier.
This will fail in the hierarchy pass (when it's implemented in a
future patch).
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cxxrtl: run hierarchy pass regardless of (*top*) attribute presence
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The hierarchy pass does a lot more than just finding the top module,
mainly resolving implicit (positional, wildcard) module connections.
Fixes #2589.
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cxxrtl: emit debug items for unused public wires
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This greatly improves debug information coverage.
Fixes #2500.
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cxxrtl: don't expect user cell inputs to be wires
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Ports can be connected to constants, too. (Usually resets.)
Fixes #2521.
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cxxrtl: don't mark buffered internal wires as UNUSED for debug
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Public wires may alias buffered internal wires, so keep BUFFERED
wires in debug information even if they are private. Debug items are
only created for public wires, so this does not otherwise affect how
debug information is emitted.
Fixes #2540.
Fixes #2841.
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cxxrtl: mark dead local wires as unused even with inlining disabled
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Fixes #2739.
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- preserve signedness of struct members
- fix initial width detection of struct members (e.g., in case expressions)
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I think the code is now a bit easier to follow (and has lost some
levels of indentation!).
The only non-trivial change is that I removed the check for
cell->type[0] != '$' when deciding whether to complain if we couldn't
find a module. This will always be true because of the early exit
earlier in the function.
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Delete unused found_init variable
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Spotted during compilation:
passes/proc/proc_init.cc: In function ‘void {anonymous}::proc_init(Yosys::RTLIL::Module*, Yosys::SigMap&, Yosys::RTLIL::Process*)’:
passes/proc/proc_init.cc:31:7: warning: variable ‘found_init’ set but not used [-Wunused-but-set-variable]
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While this helper is already useful to squash sequential initializations
into one in cxxrtl, its main purpose is to squash overlapping masked memory
initializations (when they land) and avoid having to deal with them in
cxxrtl runtime.
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This *only* does conversion, but doesn't add any new functionality —
support for memory read port init/reset is still upcoming.
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- add a backlink to module from Process
- make constructor and destructor protected, expose Module functions
to add and remove processes
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Fixes #2061.
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