iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	abc9_ops: suppress -prep_box warning for abc9_flop	Eddie Hung	2020-02-27	1	-1/+1
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*	xilinx: Update RAMB* specify entries	Eddie Hung	2020-02-27	1	-11/+42
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*	ice40: add delays to SB_CARRY	Eddie Hung	2020-02-27	1	-0/+30
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*	xilinx: add delays to INV	Eddie Hung	2020-02-27	1	-0/+3
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*	Make TimingInfo::TimingInfo(SigBit) constructor explicit	Eddie Hung	2020-02-27	3	-8/+9
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*	TimingInfo: index by (port_name,offset)	Eddie Hung	2020-02-27	2	-12/+23
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*	Fix spacing	Eddie Hung	2020-02-27	2	-68/+68
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*	More +/ice40/cells_sim.v fixes	Eddie Hung	2020-02-27	1	-27/+27
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*	Cleanup tests	Eddie Hung	2020-02-27	2	-1/+1
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*	Update bug1630.ys to use -lut 4 instead of lut file	Eddie Hung	2020-02-27	1	-1/+1
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*	Make +/xilinx/cells_sim.v legal	Eddie Hung	2020-02-27	1	-76/+78
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*	abc9_ops: still emit delay table even box has no timing	Eddie Hung	2020-02-27	1	-3/+1
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*	write_xaiger: add comment about arrival times of flop outputs	Eddie Hung	2020-02-27	1	-0/+1
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*	abc9_ops: demote lack of box timing info to warning	Eddie Hung	2020-02-27	1	-2/+4
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*	Get rid of (* abc9_{arrival,required} *) entirely	Eddie Hung	2020-02-27	6	-651/+530
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*	abc9_ops: use TimingInfo for -prep_{lut,box} too	Eddie Hung	2020-02-27	2	-25/+22
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*	abc9_ops: use TimingInfo for -prep_{lut,box} too	Eddie Hung	2020-02-27	3	-97/+65
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*	abc9_ops: add and use new TimingInfo struct	Eddie Hung	2020-02-27	2	-70/+214
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*	Fix tests/arch/xilinx/fsm.ys to count flops only	Eddie Hung	2020-02-27	1	-9/+3
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*	Expand +/xilinx/cells_sim.v to keep ICARUS and non -specify paresr happy	Eddie Hung	2020-02-27	1	-14/+12
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*	ice40: fix specify for inverted clocks	Eddie Hung	2020-02-27	1	-27/+27
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*	Fix tests by gating some specify constructs from iverilog	Eddie Hung	2020-02-27	1	-0/+16
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*	Update simple_abc9 tests	Eddie Hung	2020-02-27	3	-5/+8
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*	abc9_ops: ignore (* abc9_flop *) if not '-dff'	Eddie Hung	2020-02-27	4	-104/+114
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*	ice40: specify fixes	Eddie Hung	2020-02-27	3	-66/+66
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*	abc9_ops: sort LUT delays to be ascending	Eddie Hung	2020-02-27	1	-1/+4
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*	ice40: move over to specify blocks for -abc9	Eddie Hung	2020-02-27	10	-164/+1344
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*	synth_ecp5: use +/abc9_model.v	Eddie Hung	2020-02-27	1	-1/+1
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*	Update xilinx for ABC9	Eddie Hung	2020-02-27	3	-20/+16
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*	Create +/abc9_model.v for $__ABC9_{DELAY,FF_}	Eddie Hung	2020-02-27	2	-0/+11
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*	abc9_ops: output LUT area	Eddie Hung	2020-02-27	1	-6/+6
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*	ecp5: remove small LUT entries	Eddie Hung	2020-02-27	1	-24/+6
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*	abc9_ops: cope with T_LIMIT{,2}_{MIN,TYP,MAX} and auto-gen small LUTs	Eddie Hung	2020-02-27	1	-18/+33
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*	Fix commented out specify statement	Eddie Hung	2020-02-27	1	-6/+6
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*	xilinx: improve specify functionality	Eddie Hung	2020-02-27	8	-466/+547
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*	ecp5: deprecate abc9_{arrival,required} and *.{lut,box}	Eddie Hung	2020-02-27	7	-86/+120
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*	xilinx: use specify blocks in place of abc9_{arrival,required}	Eddie Hung	2020-02-27	3	-347/+670
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*	Auto-generate .box/.lut files from specify blocks	Eddie Hung	2020-02-27	8	-466/+268
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*	abc9_ops: assert on $specify2 properties	Eddie Hung	2020-02-27	1	-0/+3
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*	abc9_ops: -prep_box, to be called once	Eddie Hung	2020-02-27	3	-51/+50
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*	abc9_ops: -prep_lut and -write_lut to auto-generate LUT library	Eddie Hung	2020-02-27	4	-10/+200
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*	Merge pull request #1709 from rqou/coolrunner2_counter	Claire Wolf	2020-02-27	4	-97/+519
\|\ \| \| \| \|	Improve CoolRunner-II optimization by using extract_counter pass
\| *	coolrunner2: Use extract_counter to optimize counters	R. Ou	2020-02-17	3	-0/+165
\| \| \| \| \| \| \| \| \| \|	This tends to make much more efficient pterm usage compared to just throwing the problem at ABC
\| *	extract_counter: Implement extracting up counters	R. Ou	2020-02-17	1	-65/+247
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\| *	extract_counter: Add support for inverted clock enable	R. Ou	2020-02-17	1	-8/+28
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\| *	extract_counter: Fix clock enable	R. Ou	2020-02-17	1	-1/+3
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\| *	extract_counter: Fix outputting count to module port	R. Ou	2020-02-17	1	-8/+20
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\| *	extract_counter: Allow forbidding async reset	R. Ou	2020-02-17	1	-2/+17
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\| *	extract_counter: Refactor out extraction settings into struct	R. Ou	2020-02-17	1	-17/+43
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* \|	Merge pull request #1708 from rqou/coolrunner2-buf-fix	Claire Wolf	2020-02-27	4	-54/+163
\|\ \ \| \| \| \| \| \|	coolrunner2: Separate and improve buffer cell insertion pass