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* opt_clean: Add missing assignments to opt.did_something.Marcelina Kościelnicka2020-04-151-0/+6
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* Merge pull request #1918 from whitequark/simplify-improve_enumwhitequark2020-04-152-7/+5
|\ | | | | ast/simplify: improve enum handling
| * ast/simplify: improve enum handling.whitequark2020-04-152-7/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before this commit, enum values were serialized as attributes of form \enum_<width>_<value> where <value> was a decimal signed integer. This has multiple drawbacks: * Enums with large values would be hard to process for downstream tooling that cannot parse arbitrary precision decimals. (In fact Yosys also did not correctly process enums with large values, and would overflow `int`.) * Enum value attributes were not confined to their own namespace, making it harder for downstream tooling to enumerate all such attributes, as opposed to looking up any specific value. * Enum values could not include x or z, which are explicitly permitted in the SystemVerilog standard. After this commit, enum values are serialized as attributes of form \enum_value_<value> where <value> is a bit sequence of the appropriate width.
* | synth_intel_alm: VQM supportDan Ravensloft2020-04-152-6/+3
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* | setundef: Improve error messages.Marcelina Kościelnicka2020-04-151-10/+12
| | | | | | | | Fixes #1092.
* | json: Update format documentation.Marcelina Kościelnicka2020-04-151-12/+32
| | | | | | | | Fixes #1693.
* | Merge pull request #1930 from YosysHQ/claire/fix1876Claire Wolf2020-04-152-7/+73
|\ \ | | | | | | Fix handling of ternary with constant condition
| * | tests: add testcases from #1876Eddie Hung2020-04-141-0/+60
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| * | Fix 5bba9c3, closes #1876Claire Wolf2020-04-141-7/+13
| | | | | | | | | | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
* | | synth_intel_alm: alternative synthesis for Intel FPGAsDan Ravensloft2020-04-1529-1/+1662
| | | | | | | | | | | | | | | | | | | | | | | | By operating at a layer of abstraction over the rather clumsy Intel primitives, we can avoid special hacks like `dffinit -highlow` in favour of simple techmapping. This also makes the primitives much easier to manipulate, and more descriptive (no more cyclonev_lcell_comb to mean anything from a LUT2 to a LUT6).
* | | abc9_ops: Add a check ensuring that connected port actually exists.Marcelina Kościelnicka2020-04-151-0/+3
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* | | Merge pull request #1932 from YosysHQ/dave/cxxrtl-unclocked-readwhitequark2020-04-151-2/+3
|\ \ \ | | | | | | | | cxxrtl: Fix handling of unclocked memory read ports
| * | | cxxrtl: Fix handling of unclocked memory read portsDavid Shah2020-04-141-2/+3
| |/ / | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* / / opt_expr: Add more $alu optimizations.Marcelina Kościelnicka2020-04-142-23/+162
|/ / | | | | | | | | | | | | | | | | | | | | Detect the places in the $alu where the carry bit is constant (due to const A[i] == B[i] ^ BI) and split it into smaller $alu at these points. Also, make the existing const-carry detection for low bits more generic (now handles cases where both BI and CI are constant, but not equal to one another). Fixes #1912.
* | dffinit: Avoid setting init parameter to zero-length value.Marcelina Kościelnicka2020-04-142-3/+30
| | | | | | | | Fixes #1704.
* | abc9_exe: verify -> &verify -sEddie Hung2020-04-141-2/+2
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* | techmap: fix error messageEddie Hung2020-04-141-1/+1
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* | Merge pull request #1922 from whitequark/write_cxxrtl-disconnected-outputswhitequark2020-04-141-0/+2
|\ \ | | | | | | write_cxxrtl: ignore disconnected module ports
| * | write_cxxrtl: ignore disconnected module ports.whitequark2020-04-141-0/+2
| |/ | | | | | | | | | | E.g. port `q` in `submod x(.p(p), .q());`. Fixes #1920.
* | Merge pull request #1921 from whitequark/write_cxxrtl-separate-compilationwhitequark2020-04-142-10/+82
|\ \ | | | | | | write_cxxrtl: enable separate compilation
| * | write_verilog: fix precondition check.whitequark2020-04-141-1/+1
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| * | write_cxxrtl: enable separate compilation.whitequark2020-04-141-9/+81
| |/ | | | | | | | | | | This commit makes it possible to use several cxxrtl-generated files in one application, as well as compiling cxxrtl-generated code as a separate compilation unit.
* | Merge pull request #1917 from YosysHQ/eddie/abc9_delay_checkEddie Hung2020-04-141-0/+4
|\ \ | | | | | | xaiger: add check for $__ABC9_DELAY model
| * | xaiger: add check for $__ABC9_DELAY modelEddie Hung2020-04-131-0/+4
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* | | Merge pull request #1879 from jjj11x/jjj11x/package_declwhitequark2020-04-143-4/+33
|\ \ \ | | | | | | | | support using previously declared types/localparams/parameters in package
| * | | support using previously declared types/localparams/params in packageJeff Wang2020-04-073-4/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | (parameters in systemverilog packages can't actually be overridden, so allowing parameters in addition to localparams doesn't actually add any new functionality, but it's useful to be able to use the parameter keyword also)
* | | | Merge pull request #1880 from jjj11x/duplicate_enumwhitequark2020-04-141-2/+3
|\ \ \ \ | |_|_|/ |/| | | duplicated enum item names should result in an error
| * | | duplicated enum item names should result in an errorJeff Wang2020-04-071-2/+3
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* | | Merge pull request #1568 from YosysHQ/eddie/fix_zinitEddie Hung2020-04-132-17/+90
|\ \ \ | |_|/ |/| | zinit: fixes for $_DFF_[NP][NP][01]_and $adff cells with init = 1'b1
| * | zinit: resolve one more comment by @mwkmwkmwkEddie Hung2020-04-132-4/+13
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| * | zinit: fix review comments from @mwkmwkmwkEddie Hung2020-04-132-9/+37
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| * | tests: zinit on $adffEddie Hung2020-04-131-19/+18
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| * | zinit: operate on $adff, erase (* init *) entries on consumptionEddie Hung2020-04-131-22/+20
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| * | Fix S/R comment; thanks @mwkmwkmwkEddie Hung2020-04-131-1/+1
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| * | zinit to transform set/reset value of $_DFF_[NP][NP][01]_Eddie Hung2020-04-131-0/+14
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| * | Add testcase for $_DFF_[NP][NP][01]_Eddie Hung2020-04-131-0/+24
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| * | Supress error for unhandled \init if whole module selectedEddie Hung2020-04-131-3/+4
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* | opt_expr: Optimize multiplications with low 0 bits in operands.Marcelina Kościelnicka2020-04-132-0/+61
| | | | | | | | Fixes #1500.
* | Merge pull request #1910 from boqwxp/cleanup_ilang_parserwhitequark2020-04-131-4/+4
|\ \ | | | | | | Clean up pseudo-private member usage in `frontends/ilang/ilang_parser.y`.
| * | Clean up pseudo-private member usage in `frontends/ilang/ilang_parser.y`.Alberto Gonzalez2020-04-131-4/+4
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* | | Add .gitignore to tests/select/Xiretza2020-04-121-0/+1
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* | | Merge pull request #1907 from YosysHQ/dave/fix-1906David Shah2020-04-121-1/+0
|\ \ \ | | | | | | | | verilog: Fix write to deleted object
| * | | verilog: Fix write to deleted objectDavid Shah2020-04-121-1/+0
|/ / / | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | Merge pull request #1603 from whitequark/ice40-ram_stylewhitequark2020-04-1012-50/+836
|\ \ \ | | | | | | | | ice40/ecp5: add support for both 1364.1 and Synplify/LSE RAM/ROM attributes
| * | | ecp5: do not map FFRAM if explicitly requested otherwise.whitequark2020-04-032-17/+65
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| * | | ice40: do not map FFRAM if explicitly requested otherwise.whitequark2020-04-032-9/+31
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| * | | memory_map: add -attr option, to respect inference attributes.whitequark2020-04-031-6/+113
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before this commit, memory_map (which is always a part of a synth script) would always pick up any $mem cell that was not processed by a preceding pass and lower it down to $dff/$mux cells. This is undesirable for two reasons: * If there is an explicit inference attribute set on a $mem cell, e.g. (* ram_block *), then it is arguably incorrect to map such a memory to $dff/$mux cells. * If memory_map tries to lower a memory that was intended to be mapped to a large BRAM, it often takes extraordinarily long time to finish, produces an extremely large log file, and outputs an unusable design. After this commit, properly invoked memory_map will not map any memory that has an explicit inference attribute specified, solving the first issue, and alleviating the second. The default behavior is not changed.
| * | | ecp5: add support for both 1364.1 and LSE RAM/ROM attributes.whitequark2020-02-065-5/+376
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit tries to carefully follow the documented behavior of LSE and Synplify. It will use `syn_ramstyle` attribute if there are any write ports, and `syn_romstyle` attribute otherwise. * LSE supports both `syn_ramstyle` and `syn_romstyle`. * Synplify only supports `syn_ramstyle`, with same values as LSE. * Synplify also supports `syn_rw_conflict_logic`, which is not documented as supported for LSE. Limitations of the Yosys implementation: * LSE/Synplify support `syn_ramstyle="block_ram,no_rw_check"` syntax to turn off insertion of transparency logic. There is currently no way to support multiple valued attributes in memory_bram. It is also not clear if that is a good idea, since it can cause sim/synth mismatches. * LSE/Synplify/1364.1 support block ROM inference from full case statements. Yosys does not currently perform this transformation. * LSE/Synplify propagate `syn_ramstyle`/`syn_romstyle` attributes from the module to the inner memories. There is currently no way to do this in Yosys (attrmvcp only works on cells and wires).
| * | | ice40: match memory inference attribute values case insensitive.whitequark2020-02-062-0/+7
| | | | | | | | | | | | | | | | LSE/Synplify use case insensitive matching.
| * | | memory_bram: add `attr_icase` option.whitequark2020-02-061-7/+35
| | | | | | | | | | | | | | | | | | | | Some vendor toolchains use case insensitive matching for values of attributes that control BRAM inference.
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