| Commit message (Expand) | Author | Age | Files | Lines |
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| * | abc9 to replace $_NOT_ with $lut | Eddie Hung | 2019-02-19 | 1 | -4/+39 |
| * | read_aiger to create sane $lut names, and rename when renaming driving wire | Eddie Hung | 2019-02-19 | 1 | -2/+11 |
| * | Add comment | Eddie Hung | 2019-02-19 | 1 | -1/+2 |
| * | Get rid of boost dep, fix the FIXMEs for Win32? | Eddie Hung | 2019-02-19 | 1 | -14/+14 |
| * | Get rid of debugging stuff in abc9 | Eddie Hung | 2019-02-16 | 1 | -6/+1 |
| * | In read_xaiger, do not construct ConstEval for every LUT | Eddie Hung | 2019-02-16 | 1 | -1/+1 |
| * | Cleanup | Eddie Hung | 2019-02-16 | 1 | -4/+5 |
| * | read_aiger to ignore output = input of same wire; also create new output for ... | Eddie Hung | 2019-02-16 | 1 | -2/+16 |
| * | Cleanup | Eddie Hung | 2019-02-16 | 1 | -2/+1 |
| * | write_xaiger to support non-bit cell connections, and cope with COs for -O | Eddie Hung | 2019-02-16 | 1 | -13/+15 |
| * | abc9 to write_aiger with -O option, and ignore dummy outputs | Eddie Hung | 2019-02-16 | 1 | -2/+8 |
| * | write_aiger -O to write dummy output as __dummy_o__ | Eddie Hung | 2019-02-16 | 1 | -2/+5 |
| * | abc9 to handle comb loops, cope with constant outputs, disconnect using new wire | Eddie Hung | 2019-02-16 | 1 | -4/+67 |
| * | read_aiger to disable log_debug | Eddie Hung | 2019-02-16 | 1 | -1/+2 |
| * | expose command to not skip 'internal' wires beginning with '$' | Eddie Hung | 2019-02-16 | 1 | -1/+1 |
| * | read_xaiger() to use f.read() not readsome() | Eddie Hung | 2019-02-16 | 1 | -1/+2 |
| * | abc9 to cope with non-wideports, count cells properly | Eddie Hung | 2019-02-16 | 1 | -11/+54 |
| * | Tidy up write_xaiger | Eddie Hung | 2019-02-16 | 1 | -8/+6 |
| * | write_aiger() to perform CI/CO post-processing and fix symbols | Eddie Hung | 2019-02-16 | 1 | -7/+17 |
| * | read_aiger() to cope with constant outputs, mixed wideports, do cleaning | Eddie Hung | 2019-02-16 | 1 | -8/+130 |
| * | Move lookup inside if | Eddie Hung | 2019-02-15 | 1 | -2/+2 |
| * | Fixes needed for DFF circuits | Eddie Hung | 2019-02-15 | 1 | -4/+3 |
| * | Refactor | Eddie Hung | 2019-02-15 | 1 | -29/+32 |
| * | Cope with width != 1 when re-mapping cells | Eddie Hung | 2019-02-15 | 1 | -11/+25 |
| * | abc9 to stitch results with CI/CO properly | Eddie Hung | 2019-02-15 | 1 | -16/+32 |
| * | read_aiger with more asserts, and call clean | Eddie Hung | 2019-02-15 | 1 | -4/+11 |
| * | write_xaiger to cope with unknown cells by transforming them to CI/CO | Eddie Hung | 2019-02-15 | 1 | -6/+44 |
| * | More cleanup | Eddie Hung | 2019-02-14 | 1 | -15/+6 |
| * | More cleanup of write_xaiger | Eddie Hung | 2019-02-14 | 1 | -73/+1 |
| * | Get rid of formal stuff from xaiger backend | Eddie Hung | 2019-02-14 | 1 | -58/+0 |
| * | synth_ice40 to have new -abc9 arg | Eddie Hung | 2019-02-14 | 1 | -4/+12 |
| * | Leave FIXME for clean | Eddie Hung | 2019-02-13 | 1 | -3/+3 |
| * | Use module->addLut() | Eddie Hung | 2019-02-13 | 1 | -5/+1 |
| * | Fix stitching | Eddie Hung | 2019-02-13 | 1 | -4/+4 |
| * | Use ConstEval to compute LUT masks | Eddie Hung | 2019-02-13 | 2 | -63/+69 |
| * | Merge remote-tracking branch 'origin/read_aiger' into xaig | Eddie Hung | 2019-02-13 | 4 | -17/+12 |
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| | * | Missing headers for Xcode? | Eddie Hung | 2019-02-12 | 1 | -0/+2 |
| | * | Merge branch 'read_aiger' of github.com:eddiehung/yosys into read_aiger | Eddie Hung | 2019-02-12 | 1 | -3/+1 |
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| | | * | Do not break for constraints | Eddie Hung | 2019-02-11 | 1 | -1/+0 |
| | | * | No increment line_count for binary ANDs | Eddie Hung | 2019-02-11 | 1 | -1/+1 |
| | | * | Do not ignore newline after AND in binary AIG | Eddie Hung | 2019-02-11 | 1 | -1/+0 |
| | * | | Use module->add{Not,And}Gate() functions | Eddie Hung | 2019-02-12 | 1 | -8/+2 |
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| | * | Merge remote-tracking branch 'origin/dff_init' into read_aiger | Eddie Hung | 2019-02-08 | 2 | -7/+7 |
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| | | * | Cope WIDTH of ff/latch cells is default of zero | Eddie Hung | 2019-02-06 | 1 | -6/+6 |
| | | * | Remove check for cell->name[0] == '$' | Eddie Hung | 2019-02-06 | 1 | -1/+1 |
| * | | | Merge https://github.com/YosysHQ/yosys into xaig | Eddie Hung | 2019-02-13 | 3 | -44/+47 |
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| | * | | | Fix sign handling of real constants | Clifford Wolf | 2019-02-13 | 1 | -5/+4 |
| | * | | | Merge pull request #802 from whitequark/write_verilog_async_mem_ports | Clifford Wolf | 2019-02-12 | 1 | -38/+41 |
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| | | * | | | write_verilog: correctly emit asynchronous transparent ports. | whitequark | 2019-01-29 | 1 | -38/+41 |
| | * | | | | Merge pull request #806 from daveshah1/fsm_opt_no_reset | Clifford Wolf | 2019-02-12 | 1 | -1/+2 |
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