| Commit message (Collapse) | Author | Age | Files | Lines | ||
|---|---|---|---|---|---|---|
| ... | ||||||
| | * | | Allow defining input ports as "input logic" in SystemVerilog | Ruben Undheim | 2016-06-20 | 1 | -2/+2 | |
| |/ / | ||||||
| * | | Bugfix in "abc -script" handling | Clifford Wolf | 2016-06-19 | 1 | -53/+50 | |
| | | | ||||||
| * | | Merge branch 'sv_packages' of https://github.com/rubund/yosys | Clifford Wolf | 2016-06-19 | 7 | -1/+52 | |
| |\ \ | ||||||
| | * | | A few modifications after pull request comments | Ruben Undheim | 2016-06-18 | 3 | -5/+4 | |
| | | | | | | | | | | | | | | | | - Renamed Design::packages to Design::verilog_packages - No need to include ast.h in rtlil.h | |||||
| | * | | Added support for SystemVerilog packages with localparam definitions | Ruben Undheim | 2016-06-18 | 7 | -1/+53 | |
| | | | | ||||||
| * | | | Added "deminout" | Clifford Wolf | 2016-06-19 | 3 | -0/+118 | |
| | | | | ||||||
| * | | | Added "read_blif -sop" | Clifford Wolf | 2016-06-18 | 1 | -5/+10 | |
| | | | | ||||||
| * | | | Added $sop support to BLIF back-end | Clifford Wolf | 2016-06-18 | 1 | -2/+29 | |
| |/ / | ||||||
| * | | Added "dc2" to default ABC scripts | Clifford Wolf | 2016-06-17 | 1 | -5/+5 | |
| | | | ||||||
| * | | Fixed init issue in mem2reg_test2 test case | Clifford Wolf | 2016-06-17 | 1 | -2/+6 | |
| | | | ||||||
| * | | Added "abc -I <num> -P <num>" | Clifford Wolf | 2016-06-17 | 1 | -8/+33 | |
| | | | ||||||
| * | | Added $sop SAT model | Clifford Wolf | 2016-06-17 | 1 | -0/+82 | |
| | | | ||||||
| * | | Improved support for $sop cells | Clifford Wolf | 2016-06-17 | 6 | -10/+89 | |
| | | | ||||||
| * | | Added $sop cell type and "abc -sop" | Clifford Wolf | 2016-06-17 | 7 | -31/+171 | |
| | | | ||||||
| * | | Updated ABC to hg rev b5df6e2b76f0 | Clifford Wolf | 2016-06-17 | 2 | -10/+10 | |
| | | | ||||||
| * | | Added "nlutmap -assert" | Clifford Wolf | 2016-06-09 | 2 | -3/+17 | |
| | | | ||||||
| * | | Do not run "wreduce" in "prep -ifx" | Clifford Wolf | 2016-06-08 | 1 | -2/+3 | |
| | | | ||||||
| * | | Added "proc_mux -ifx" | Clifford Wolf | 2016-06-06 | 3 | -21/+54 | |
| | | | ||||||
| * | | Added "setundef -init" | Clifford Wolf | 2016-06-03 | 1 | -5/+89 | |
| | | | ||||||
| * | | Fix all undef-muxes in dlatch input cone | Clifford Wolf | 2016-06-02 | 1 | -34/+72 | |
| | | | ||||||
| * | | Avoid creating undef-muxes when inferring latches in proc_dlatch | Clifford Wolf | 2016-06-01 | 1 | -0/+44 | |
| | | | ||||||
| * | | Added opt_expr support for div/mod by power-of-two | Clifford Wolf | 2016-05-29 | 2 | -0/+96 | |
| | | | ||||||
| * | | Fixed procedural assignments to non-unique lvalues, e.g. {y,y} = {a,b} | Clifford Wolf | 2016-05-27 | 1 | -0/+11 | |
| | | | ||||||
| * | | Fixed access-after-delete bug in mem2reg code | Clifford Wolf | 2016-05-27 | 2 | -6/+23 | |
| | | | ||||||
| * | | fixed typos in error messages | Clifford Wolf | 2016-05-27 | 1 | -3/+3 | |
| | | | ||||||
| * | | Fixed "scc" for cells that have feedback singals _and_ are part of a larger loop | Clifford Wolf | 2016-05-27 | 1 | -3/+3 | |
| | | | ||||||
| * | | Merge pull request #172 from zeldin/deterministic_hierarchy | Clifford Wolf | 2016-05-22 | 1 | -3/+3 | |
| |\ \ | | | | | | | Made the expansion order of hierarchy deterministic | |||||
| | * | | Made the expansion order of hierarchy deterministic | Marcus Comstedt | 2016-05-22 | 1 | -3/+3 | |
| |/ / | ||||||
| * | | Some fixes in tests/asicworld/*_tb.v | Clifford Wolf | 2016-05-20 | 4 | -50/+41 | |
| | | | ||||||
| * | | Improvements and fixes in autotest.sh script and test_autotb | Clifford Wolf | 2016-05-20 | 2 | -9/+9 | |
| | | | ||||||
| * | | Merge branch 'master' of https://github.com/Kmanfi/yosys | Clifford Wolf | 2016-05-20 | 2 | -11/+18 | |
| |\ \ | ||||||
| | * | | Close opened dump file. | Kaj Tuomi | 2016-05-19 | 1 | -0/+1 | |
| | | | | ||||||
| | * | | Fix for Modelsim transcript line warp issue #164 | Kaj Tuomi | 2016-05-19 | 2 | -11/+17 | |
| | | | | ||||||
| * | | | Also escape "=" in spice output | Clifford Wolf | 2016-05-20 | 1 | -1/+1 | |
| | | | | ||||||
| * | | | Small improvements in Verilog front-end docs | Clifford Wolf | 2016-05-20 | 2 | -0/+8 | |
| |/ / | ||||||
| * | | Don't sign-extend memory bram initialization data | Clifford Wolf | 2016-05-15 | 1 | -1/+1 | |
| | | | ||||||
| * | | Added missing "#define HASHLIB_H" | Clifford Wolf | 2016-05-14 | 1 | -0/+1 | |
| | | | ||||||
| * | | Minor presentation fixes | Clifford Wolf | 2016-05-14 | 1 | -1/+1 | |
| | | | ||||||
| * | | Updated min GCC requirement to GCC 4.8 | Clifford Wolf | 2016-05-11 | 2 | -14/+14 | |
| | | | ||||||
| * | | Added manual download link to README | Clifford Wolf | 2016-05-09 | 1 | -0/+4 | |
| | | | ||||||
| * | | Include <cmath> in yosys.h | Clifford Wolf | 2016-05-08 | 2 | -9/+1 | |
| | | | ||||||
| * | | Merge pull request #162 from azonenberg/master | Clifford Wolf | 2016-05-08 | 1 | -2/+33 | |
| |\ \ | | | | | | | Added GP_DELAY cell. Fixed several errors in simulation models. | |||||
| | * | | Added GP_DELAY cell | Andrew Zonenberg | 2016-05-07 | 1 | -0/+29 | |
| | | | | ||||||
| | * | | Fixed typo in port name | Andrew Zonenberg | 2016-05-07 | 1 | -1/+1 | |
| | | | | ||||||
| | * | | Fixed extra semicolon | Andrew Zonenberg | 2016-05-07 | 1 | -1/+1 | |
| | | | | ||||||
| | * | | Fixed typo in parameter name | Andrew Zonenberg | 2016-05-07 | 1 | -1/+1 | |
| | | | | ||||||
| | * | | Added simulation timescale declaration | Andrew Zonenberg | 2016-05-07 | 1 | -0/+2 | |
| |/ / | ||||||
| * | | Fixes for MXE build | Clifford Wolf | 2016-05-07 | 3 | -10/+10 | |
| | | | ||||||
| * | | Added support for "keep" attribute to shregmap | Clifford Wolf | 2016-05-07 | 1 | -2/+2 | |
| | | | ||||||
| * | | Added synth_ice40 support for latches via logic loops | Clifford Wolf | 2016-05-06 | 3 | -0/+13 | |
| | | | ||||||
 |
index : iCE40/yosys | |
| [no description] |
| aboutsummaryrefslogtreecommitdiffstats |