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* Use C++11 final/override keywords.whitequark2020-06-18220-548/+540
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* Merge pull request #2153 from boqwxp/splitnets-cleanupN. Engelhardt2020-06-181-16/+19
|\ | | | | splitnets: Cleanup and efficiency improvements
| * splitnets: Clean up pseudo-private member usageAlberto Gonzalez2020-06-131-7/+6
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| * splitnets: Slightly improve efficiency by avoiding some unnecessary lookupsAlberto Gonzalez2020-06-131-9/+13
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* | Merge pull request #2167 from whitequark/cxxrtl-fix-ndebugwhitequark2020-06-181-1/+2
|\ \ | | | | | | cxxrtl: don't compute vital values in log_assert()
| * | cxxrtl: don't compute vital values in log_assert().whitequark2020-06-171-1/+2
| | | | | | | | | | | | | | | | | | This breaks NDEBUG builds. Fixes #2166.
* | | Merge pull request #2142 from whitequark/splitnets-hdlnamewhitequark2020-06-181-0/+4
|\ \ \ | | |/ | |/| splitnets: propagate (*hdlname*) and disambiguate via start_offset
| * | splitnets: propagate (*hdlname*) and disambiguate via start_offset.whitequark2020-06-101-0/+4
| | | | | | | | | | | | This allows reliably coalescing the split wires later.
* | | Merge pull request #2164 from madebr/msvcMiodrag Milanović2020-06-184-11/+11
|\ \ \ | | | | | | | | Get yosys building on Visual Studio
| * | | msvc does not support designated initializers in structsAnonymous Maarten2020-06-171-5/+5
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| * | | MSVC does not understand __builtin_unreachableAnonymous Maarten2020-06-171-1/+1
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| * | | MSVC cannot omit operand in conditionalAnonymous Maarten2020-06-171-1/+1
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| * | | MSVC defines TRANSPARENT tooAnonymous Maarten2020-06-171-4/+4
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* | | Merge pull request #2163 from jfng/cxxrtl-blackbox-debuginfowhitequark2020-06-171-13/+17
|\ \ \ | | | | | | | | cxxrtl: restrict the debug info of a blackbox to its ports.
| * | | cxxrtl: restrict the debug info of a blackbox to its ports.Jean-François Nguyen2020-06-161-13/+17
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* | | Merge pull request #2160 from whitequark/cxxrtl-fix-warningwhitequark2020-06-171-21/+23
|\ \ \ | | | | | | | | cxxrtl: avoid unused variable warning for transparent $memrd ports
| * | | cxxrtl: avoid unused variable warning for transparent $memrd ports. NFC.whitequark2020-06-151-21/+23
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* | | | Merge pull request #2156 from XarkLabs/masterN. Engelhardt2020-06-161-7/+7
|\ \ \ \ | |_|/ / |/| | | Fix Verilator sim warnings: 1 BLKSEQ and 3 WIDTH
| * | | Fix Verilator sim warnings: 1 BLKSEQ and 3 WIDTHXark2020-06-141-7/+7
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* | | | Merge pull request #2159 from MerryMage/cxxrtl-mulwhitequark2020-06-151-17/+22
|\ \ \ \ | |_|/ / |/| | | cxxrtl: Implement chunk-wise multiplication
| * | | cxxrtl: Implement chunk-wise multiplicationMerryMage2020-06-151-17/+22
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* | | Merge pull request #2158 from miek/sshr-sign-extensionwhitequark2020-06-151-2/+4
|\ \ \ | |/ / |/| | cxxrtl: fix sshr sign-extension.
| * | cxxrtl: fix sshr sign-extension.Mike Walters2020-06-151-2/+4
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* | | Merge pull request #2155 from whitequark/fix-wasm-wasi-sdk-11whitequark2020-06-131-1/+3
|\ \ \ | | | | | | | | kernel: guard include of signal.h more precisely
| * | | kernel: guard include of signal.h more precisely.whitequark2020-06-131-1/+3
|/ / / | | | | | | | | | | | | | | | Upgrading to WASI SDK 11.0 caused the WASM build to fail because WASM does not have signals. (Arguably Yosys was broken even before, it was just broken silently.)
* | | Merge pull request #2151 from whitequark/cxxrtl-fix-rzextwhitequark2020-06-131-2/+2
|\ \ \ | |/ / |/| | cxxrtl: fix rzext()
| * | cxxrtl: fix rzext().whitequark2020-06-131-2/+2
| | | | | | | | | | | | | | | | | | | | | This was a correctness issue, but one of the consequences is that it resulted in jumps in generated machine code where there should have been none. As a side effect of fixing the bug, Minerva SoC became 10% faster.
* | | Merge pull request #2145 from whitequark/cxxrtl-splitnetswhitequark2020-06-135-67/+156
|\ \ \ | | | | | | | | cxxrtl: handle multipart signals
| * | | cxxrtl: handle multipart signals.whitequark2020-06-115-27/+94
| | | | | | | | | | | | | | | | This avoids losing design visibility when using the `splitnets` pass.
| * | | cxxrtl: expose RTLIL::{Wire,Memory}->start_offset in debug info.whitequark2020-06-113-40/+62
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* | | Merge pull request #2152 from whitequark/cxxrtl-always-inlinewhitequark2020-06-131-4/+108
|\ \ \ | |_|/ |/| | cxxrtl: always inline internal cells and slice/concat operations
| * | cxxrtl: always inline internal cells and slice/concat operations.whitequark2020-06-131-4/+108
|/ / | | | | | | | | | | This can result in massive reduction in runtime, up to 50% depending on workload. Currently people are using `-mllvm -inline-threshold=` as a workaround (with clang++), but this solution is more portable.
* | Merge pull request #2150 from whitequark/cxxrtl-elide-pmuxwhitequark2020-06-121-30/+16
|\ \ | | | | | | cxxrtl: elide $pmux cells
| * | cxxrtl: elide $pmux cells.whitequark2020-06-121-30/+16
|/ / | | | | | | | | On Minerva, this improves runtime by around 10%, mostly by ensuring that the logic driving FFs is packed into edge conditionals.
* | Merge pull request #2149 from whitequark/cxxrtl-unbuffer-outputswhitequark2020-06-121-20/+24
|\ \ | | | | | | cxxrtl: unbuffer output wires of toplevel module
| * | cxxrtl: annotate port direction as comments.whitequark2020-06-121-1/+8
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| * | cxxrtl: unbuffer output wires of toplevel module.whitequark2020-06-121-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Without unbuffering output wires of, at least, toplevel modules, it is not possible to have most designs that rely on IO via toplevel ports (as opposed to using exclusively blackboxes) converge within one delta cycle. That seriously impairs the performance of CXXRTL. This commit avoids unbuffering outputs of all modules solely so that in future, CXXRTL could gain fully separate compilation, and not for any present technical reason.
| * | cxxrtl: simplify unbuffering of input wires.whitequark2020-06-121-20/+17
| |/ | | | | | | This also fixes an edge case with (*keep*) input ports.
* / intel_alm: fix DFFE matchingDan Ravensloft2020-06-113-5/+5
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* Merge pull request #2141 from whitequark/cxxrtl-cxx11whitequark2020-06-103-8/+10
|\ | | | | cxxrtl: various compiler compatibility fixes
| * cxxrtl: restore C++11 compatibility.whitequark2020-06-101-1/+2
| | | | | | | | This is necessary to be able to build CXXRTL models via yosys-config.
| * cxxrtl: fix a few gcc warnings.whitequark2020-06-101-5/+6
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| * Fix formatting. NFC.whitequark2020-06-101-2/+2
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* | Merge pull request #2140 from whitequark/cxxrtl-aliaseswhitequark2020-06-104-9/+50
|\ \ | |/ |/| cxxrtl: disambiguate values/wires and their aliases in debug info
| * cxxrtl: disambiguate values/wires and their aliases in debug info.whitequark2020-06-104-9/+50
|/ | | | | | | With this change, it is easier to see which signals carry state (only wire<>s appear as `reg` in VCD files) and to construct a minimal checkpoint (CXXRTL_WIRE debug items represent the canonical smallest set of state required to fully reconstruct the simulation).
* Merge pull request #2134 from whitequark/cxxrtl-opt-debugwhitequark2020-06-101-52/+105
|\ | | | | cxxrtl: introduce -Og optimization level
| * cxxrtl: allow unbuffering without localizing.whitequark2020-06-091-40/+74
| | | | | | | | | | | | | | Although logically two separate steps, these were treated as one for historic reasons. Splitting the two makes it possible to have designs that are only 2× slower than fastest possible (and are without extra delta cycles) that allow probing all public wires.
| * cxxrtl: order -On levels as localize, elide instead of the reverse.whitequark2020-06-091-8/+8
| | | | | | | | | | | | | | | | | | | | | | Historically, elision was implemented before localization, so levels with elision are lower than corresponding levels with localization. This is unfortunate for two reasons: 1. Elision is a logical subset of localization, since it equals to not giving a name to a temporary. 2. "Localize" currently actually means "unbuffer and localize", and it would be useful to split those steps (at least for public wires) for improved design visibility.
| * cxxrtl: factor out -noproc/-noflatten from -O.whitequark2020-06-091-17/+36
| | | | | | | | | | | | | | | | Although these options can be thought of as optimizations, they are essentially orthogonal to the core of -O, which is managing signal buffering and scope. Going from -O4 to -O2 means going from limited to complete design visibility, yet in both cases proc and flatten are desirable.
* | Merge pull request #2131 from YosysHQ/claire/preserveffsclairexen2020-06-106-33/+50
|\ \ | | | | | | Do not optimize away FFs in "prep" and Verific front-end
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