| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| | * | | | | | | Adjusting Vivado's BRAM min bits threshold for RAMB18E1 | Diego H | 2019-11-27 | 1 | -2/+5 | |
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| * | | | | | | | abc9_map.v: fix Xilinx LUTRAM | Eddie Hung | 2019-12-12 | 1 | -6/+6 | |
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| * | | | | | | Update README.md :: abc_ -> abc9_ | Eddie Hung | 2019-12-11 | 1 | -3/+3 | |
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| * | | | | | Fix bitwidth mismatch; suppresses iverilog warning | Eddie Hung | 2019-12-11 | 1 | -4/+4 | |
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| * | | | | | Merge pull request #1564 from ZirconiumX/intel_housekeeping | David Shah | 2019-12-11 | 8 | -6/+6 | |
| |\ \ \ \ \ | | | | | | | | | | | | | Intel housekeeping | |||||
| | * | | | | | synth_intel: a10gx -> arria10gx | Dan Ravensloft | 2019-12-10 | 5 | -4/+4 | |
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| | * | | | | | synth_intel: cyclone10 -> cyclone10lp | Dan Ravensloft | 2019-12-10 | 5 | -4/+4 | |
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| * | | | | | | Merge pull request #1545 from YosysHQ/eddie/ice40_wrapcarry_attr | Eddie Hung | 2019-12-09 | 8 | -51/+225 | |
| |\ \ \ \ \ \ | |_|_|_|/ / |/| | | | | | Preserve SB_CARRY name and attributes when using $__ICE40_CARRY_WRAPPER | |||||
| | * | | | | | ice40_opt to restore attributes/name when unwrapping | Eddie Hung | 2019-12-09 | 1 | -0/+15 | |
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| | * | | | | | ice40_wrapcarry -unwrap to preserve 'src' attribute | Eddie Hung | 2019-12-09 | 1 | -1/+9 | |
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| | * | | | | | unmap $__ICE40_CARRY_WRAPPER in test | Eddie Hung | 2019-12-09 | 1 | -1/+21 | |
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| | * | | | | | -unwrap to create $lut not SB_LUT4 for opt_lut | Eddie Hung | 2019-12-09 | 1 | -7/+5 | |
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| | * | | | | | Sensitive to direct inst of $__ICE40_CARRY_WRAPPER; recreate SB_LUT4 | Eddie Hung | 2019-12-09 | 2 | -8/+12 | |
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| | * | | | | | ice40_wrapcarry to really preserve attributes via -unwrap option | Eddie Hung | 2019-12-09 | 4 | -39/+61 | |
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| | * | | | | | Drop keep=0 attributes on SB_CARRY | Eddie Hung | 2019-12-06 | 2 | -2/+10 | |
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| | * | | | | | Merge SB_CARRY+SB_LUT4's attributes when creating $__ICE40_CARRY_WRAPPER | Eddie Hung | 2019-12-05 | 1 | -0/+1 | |
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| | * | | | | | Add WIP test for unwrapping $__ICE40_CARRY_WRAPPER | Eddie Hung | 2019-12-05 | 1 | -0/+30 | |
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| | * | | | | | Check SB_CARRY name also preserved | Eddie Hung | 2019-12-03 | 1 | -0/+1 | |
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| | * | | | | | $__ICE40_CARRY_WRAPPER to use _TECHMAP_REPLACE_ for SB_CARRY to preserve | Eddie Hung | 2019-12-03 | 1 | -1/+1 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | name and attr | |||||
| | * | | | | | ice40_opt to ignore (* keep *) -ed cells | Eddie Hung | 2019-12-03 | 1 | -0/+5 | |
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| | * | | | | | ice40_wrapcarry to preserve SB_CARRY's attributes | Eddie Hung | 2019-12-03 | 1 | -0/+2 | |
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| | * | | | | | Add testcase | Eddie Hung | 2019-12-03 | 1 | -0/+60 | |
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| * | | | | | | Merge pull request #1555 from antmicro/fix-macc-xilinx-test | Eddie Hung | 2019-12-06 | 1 | -1/+1 | |
| |\ \ \ \ \ \ | |_|_|_|_|/ |/| | | | | | tests: arch: xilinx: Change order of arguments in macc.sh | |||||
| | * | | | | | tests: arch: xilinx: Change order of arguments in macc.sh | Jan Kowalewski | 2019-12-06 | 1 | -1/+1 | |
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| * | | | | | Merge pull request #1551 from whitequark/manual-cell-operands | Clifford Wolf | 2019-12-05 | 3 | -43/+82 | |
| |\ \ \ \ \ | |_|/ / / |/| | | | | Clarify semantics of comb cells, in particular shifts | |||||
| | * | | | | kernel: require \B_SIGNED=0 on $shl, $sshl, $shr, $sshr. | whitequark | 2019-12-04 | 2 | -8/+26 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before this commit, these cells would accept any \B_SIGNED and in case of \B_SIGNED=1, would still treat the \B input as unsigned. Also fix the Verilog frontend to never emit such constructs. | |||||
| | * | | | | manual: document behavior of many comb cells more precisely. | whitequark | 2019-12-04 | 1 | -35/+56 | |
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| * | | | | | xilinx: Add tristate buffer mapping. (#1528) | Marcin Kościelnicki | 2019-12-04 | 2 | -9/+16 | |
| | | | | | | | | | | | | | | | | Fixes #1225. | |||||
| * | | | | | iopadmap: Refactor and fix tristate buffer mapping. (#1527) | Marcin Kościelnicki | 2019-12-04 | 2 | -146/+196 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The previous code for rerouting wires when inserting tristate buffers was overcomplicated and didn't handle all cases correctly (in particular, only cell connections were rewired — internal connections were not). | |||||
| * | | | | | xilinx: Add models for LUTRAM cells. (#1537) | Marcin Kościelnicki | 2019-12-04 | 3 | -624/+831 | |
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| * | | | | Merge pull request #1524 from pepijndevos/gowindffinit | Clifford Wolf | 2019-12-03 | 5 | -114/+571 | |
| |\ \ \ \ | | | | | | | | | | | Gowin: add and test DFF init values | |||||
| | * | | | | update test | Pepijn de Vos | 2019-12-03 | 1 | -2/+3 | |
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| | * | | | | Use -match-init to not synth contradicting init values | Pepijn de Vos | 2019-12-03 | 2 | -11/+13 | |
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| | * | | | | attempt to fix formatting | Pepijn de Vos | 2019-11-25 | 2 | -292/+292 | |
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| | * | | | | gowin: add and test dff init values | Pepijn de Vos | 2019-11-25 | 4 | -41/+495 | |
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| * | | | | | Merge pull request #1542 from YosysHQ/dave/abc9-loop-fix | David Shah | 2019-12-02 | 2 | -29/+46 | |
| |\ \ \ \ \ | | | | | | | | | | | | | abc9: Fix breaking of SCCs | |||||
| | * | | | | | abc9: Fix breaking of SCCs | David Shah | 2019-12-01 | 2 | -29/+46 | |
| | | |/ / / | |/| | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
| * | | | | | Merge pull request #1539 from YosysHQ/mwk/ilang-bounds-check | Clifford Wolf | 2019-12-01 | 1 | -0/+4 | |
| |\ \ \ \ \ | |/ / / / |/| | | | | read_ilang: do bounds checking on bit indices | |||||
| | * | | | | read_ilang: do bounds checking on bit indices | Marcin Kościelnicki | 2019-11-27 | 1 | -0/+4 | |
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| * | | | | | Merge pull request #1540 from YosysHQ/mwk/xilinx-bufpll | Miodrag Milanović | 2019-11-29 | 2 | -0/+21 | |
| |\ \ \ \ \ | | | | | | | | | | | | | xilinx: Add missing blackbox cell for BUFPLL. | |||||
| | * | | | | | xilinx: Add missing blackbox cell for BUFPLL. | Marcin Kościelnicki | 2019-11-29 | 2 | -0/+21 | |
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| * | | | | | Revert "Fold loop" | Eddie Hung | 2019-11-27 | 1 | -3/+6 | |
| | |/ / / |/| | | | | | | | | | | | This reverts commit a30d5e1cc35791a98b2269c5e587c566fe8b0a35. | |||||
| * | | | | Merge pull request #1536 from YosysHQ/eddie/xilinx_dsp_muladd | Eddie Hung | 2019-11-27 | 2 | -3/+72 | |
| |\ \ \ \ | | | | | | | | | | | xilinx_dsp: consider sign and zero-extension when packing post-multiplier adder | |||||
| | * | | | | No need for -abc9 | Eddie Hung | 2019-11-26 | 1 | -1/+1 | |
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| | * | | | | Add citation | Eddie Hung | 2019-11-26 | 1 | -0/+1 | |
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| | * | | | | Check for either sign or zero extension for postAdd packing | Eddie Hung | 2019-11-26 | 1 | -3/+3 | |
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| | * | | | | Add testcase derived from fastfir_dynamictaps benchmark | Eddie Hung | 2019-11-26 | 1 | -0/+68 | |
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| * | | | | Merge pull request #1501 from YosysHQ/dave/mem_copy_attr | Clifford Wolf | 2019-11-27 | 1 | -0/+4 | |
| |\ \ \ \ | | | | | | | | | | | memory_collect: Copy attr from RTLIL::Memory to cell | |||||
| | * | | | | memory_collect: Copy attr from RTLIL::Memory to cell | David Shah | 2019-11-18 | 1 | -0/+4 | |
| | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
| * | | | | | Merge pull request #1534 from YosysHQ/mwk/opt_share-fix | Clifford Wolf | 2019-11-27 | 2 | -4/+24 | |
| |\ \ \ \ \ | | | | | | | | | | | | | opt_share: Fix handling of fine cells. | |||||
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index : iCE40/yosys | |
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