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* Merge pull request #1921 from whitequark/write_cxxrtl-separate-compilationwhitequark2020-04-142-10/+82
|\ | | | | write_cxxrtl: enable separate compilation
| * write_verilog: fix precondition check.whitequark2020-04-141-1/+1
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| * write_cxxrtl: enable separate compilation.whitequark2020-04-141-9/+81
| | | | | | | | | | | | This commit makes it possible to use several cxxrtl-generated files in one application, as well as compiling cxxrtl-generated code as a separate compilation unit.
* | Merge pull request #1917 from YosysHQ/eddie/abc9_delay_checkEddie Hung2020-04-141-0/+4
|\ \ | | | | | | xaiger: add check for $__ABC9_DELAY model
| * | xaiger: add check for $__ABC9_DELAY modelEddie Hung2020-04-131-0/+4
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* | | Merge pull request #1879 from jjj11x/jjj11x/package_declwhitequark2020-04-143-4/+33
|\ \ \ | | | | | | | | support using previously declared types/localparams/parameters in package
| * | | support using previously declared types/localparams/params in packageJeff Wang2020-04-073-4/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | (parameters in systemverilog packages can't actually be overridden, so allowing parameters in addition to localparams doesn't actually add any new functionality, but it's useful to be able to use the parameter keyword also)
* | | | Merge pull request #1880 from jjj11x/duplicate_enumwhitequark2020-04-141-2/+3
|\ \ \ \ | |_|_|/ |/| | | duplicated enum item names should result in an error
| * | | duplicated enum item names should result in an errorJeff Wang2020-04-071-2/+3
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* | | Merge pull request #1568 from YosysHQ/eddie/fix_zinitEddie Hung2020-04-132-17/+90
|\ \ \ | |_|/ |/| | zinit: fixes for $_DFF_[NP][NP][01]_and $adff cells with init = 1'b1
| * | zinit: resolve one more comment by @mwkmwkmwkEddie Hung2020-04-132-4/+13
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| * | zinit: fix review comments from @mwkmwkmwkEddie Hung2020-04-132-9/+37
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| * | tests: zinit on $adffEddie Hung2020-04-131-19/+18
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| * | zinit: operate on $adff, erase (* init *) entries on consumptionEddie Hung2020-04-131-22/+20
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| * | Fix S/R comment; thanks @mwkmwkmwkEddie Hung2020-04-131-1/+1
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| * | zinit to transform set/reset value of $_DFF_[NP][NP][01]_Eddie Hung2020-04-131-0/+14
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| * | Add testcase for $_DFF_[NP][NP][01]_Eddie Hung2020-04-131-0/+24
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| * | Supress error for unhandled \init if whole module selectedEddie Hung2020-04-131-3/+4
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* | opt_expr: Optimize multiplications with low 0 bits in operands.Marcelina Kościelnicka2020-04-132-0/+61
| | | | | | | | Fixes #1500.
* | Merge pull request #1910 from boqwxp/cleanup_ilang_parserwhitequark2020-04-131-4/+4
|\ \ | | | | | | Clean up pseudo-private member usage in `frontends/ilang/ilang_parser.y`.
| * | Clean up pseudo-private member usage in `frontends/ilang/ilang_parser.y`.Alberto Gonzalez2020-04-131-4/+4
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* | | Add .gitignore to tests/select/Xiretza2020-04-121-0/+1
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* | | Merge pull request #1907 from YosysHQ/dave/fix-1906David Shah2020-04-121-1/+0
|\ \ \ | | | | | | | | verilog: Fix write to deleted object
| * | | verilog: Fix write to deleted objectDavid Shah2020-04-121-1/+0
|/ / / | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | Merge pull request #1603 from whitequark/ice40-ram_stylewhitequark2020-04-1012-50/+836
|\ \ \ | | | | | | | | ice40/ecp5: add support for both 1364.1 and Synplify/LSE RAM/ROM attributes
| * | | ecp5: do not map FFRAM if explicitly requested otherwise.whitequark2020-04-032-17/+65
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| * | | ice40: do not map FFRAM if explicitly requested otherwise.whitequark2020-04-032-9/+31
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| * | | memory_map: add -attr option, to respect inference attributes.whitequark2020-04-031-6/+113
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before this commit, memory_map (which is always a part of a synth script) would always pick up any $mem cell that was not processed by a preceding pass and lower it down to $dff/$mux cells. This is undesirable for two reasons: * If there is an explicit inference attribute set on a $mem cell, e.g. (* ram_block *), then it is arguably incorrect to map such a memory to $dff/$mux cells. * If memory_map tries to lower a memory that was intended to be mapped to a large BRAM, it often takes extraordinarily long time to finish, produces an extremely large log file, and outputs an unusable design. After this commit, properly invoked memory_map will not map any memory that has an explicit inference attribute specified, solving the first issue, and alleviating the second. The default behavior is not changed.
| * | | ecp5: add support for both 1364.1 and LSE RAM/ROM attributes.whitequark2020-02-065-5/+376
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit tries to carefully follow the documented behavior of LSE and Synplify. It will use `syn_ramstyle` attribute if there are any write ports, and `syn_romstyle` attribute otherwise. * LSE supports both `syn_ramstyle` and `syn_romstyle`. * Synplify only supports `syn_ramstyle`, with same values as LSE. * Synplify also supports `syn_rw_conflict_logic`, which is not documented as supported for LSE. Limitations of the Yosys implementation: * LSE/Synplify support `syn_ramstyle="block_ram,no_rw_check"` syntax to turn off insertion of transparency logic. There is currently no way to support multiple valued attributes in memory_bram. It is also not clear if that is a good idea, since it can cause sim/synth mismatches. * LSE/Synplify/1364.1 support block ROM inference from full case statements. Yosys does not currently perform this transformation. * LSE/Synplify propagate `syn_ramstyle`/`syn_romstyle` attributes from the module to the inner memories. There is currently no way to do this in Yosys (attrmvcp only works on cells and wires).
| * | | ice40: match memory inference attribute values case insensitive.whitequark2020-02-062-0/+7
| | | | | | | | | | | | | | | | LSE/Synplify use case insensitive matching.
| * | | memory_bram: add `attr_icase` option.whitequark2020-02-061-7/+35
| | | | | | | | | | | | | | | | | | | | Some vendor toolchains use case insensitive matching for values of attributes that control BRAM inference.
| * | | ice40: add support for both 1364.1 and LSE RAM/ROM attributes.whitequark2020-02-064-20/+238
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit tries to carefully follow the documented behavior of LSE and Synplify. It will use `syn_ramstyle` attribute if there are any write ports, and `syn_romstyle` attribute otherwise. * LSE supports both `syn_ramstyle` and `syn_romstyle`. * Synplify only supports `syn_ramstyle`, with same values as LSE. * Synplify also supports `syn_rw_conflict_logic`, which is not documented as supported for LSE. Limitations of the Yosys implementation: * LSE/Synplify appear to interpret attribute values insensitive to case. There is currently no way to do this in Yosys (attrmap can only change case of attribute names). * LSE/Synplify support `syn_ramstyle="block_ram,no_rw_check"` syntax to turn off insertion of transparency logic. There is currently no way to support multiple valued attributes in memory_bram. It is also not clear if that is a good idea, since it can cause sim/synth mismatches. * LSE/Synplify/1364.1 support block ROM inference from full case statements. Yosys does not currently perform this transformation. * LSE/Synplify propagate `syn_ramstyle`/`syn_romstyle` attributes from the module to the inner memories. There is currently no way to do this in Yosys (attrmvcp only works on cells and wires).
| * | | ice40: remove impossible test.whitequark2020-02-061-15/+0
| | | | | | | | | | | | | | | | | | | | | | | | iCE40 does not have LUTRAM. This was erroneously added in commit caab66111e2b5052bd26c8fd64b1324e7e4a4106, and tested for BRAM, essentially a duplicate of the "dpram.ys" test.
* | | | Merge pull request #1893 from mmicko/program_prefixMiodrag Milanović2020-04-1010-65/+75
|\ \ \ \ | |_|/ / |/| | | Support custom PROGRAM_PREFIX
| * | | Keep libyosys name same as befire, but put it in directoryMiodrag Milanovic2020-04-101-11/+11
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| * | | Support custom PROGRAM_PREFIXMiodrag Milanovic2020-04-1010-71/+81
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* | | Merge pull request #1562 from whitequark/write_cxxrtlwhitequark2020-04-106-0/+2834
|\ \ \ | | | | | | | | write_cxxrtl: new backend
| * | | write_cxxrtl: add basic documentation.whitequark2020-04-091-1/+16
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| * | | write_cxxrtl: add support for $dlatch and $dlatchsr cells.whitequark2020-04-091-3/+16
| | | | | | | | | | | | | | | | Also, fix codegen for $dffe and $adff.
| * | | write_cxxrtl: add support for $sr cell.whitequark2020-04-091-27/+35
| | | | | | | | | | | | | | | | | | | | | | | | Also, fix the semantics of SET/CLR inputs of the $dffsr cell, and fix the scheduling of async FF cells to consider ARST/SET/CLR->Q as a forward combinatorial arc.
| * | | write_cxxrtl: add support for $slice and $concat cells.whitequark2020-04-091-1/+16
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| * | | write_cxxrtl: improve writable memory handling.whitequark2020-04-092-65/+87
| | | | | | | | | | | | | | | | | | | | | | | | This commit reduces space and time overhead for writable memories to O(write port count) in both cases; implements handling for write port priorities; and simplifies runtime representation of memories.
| * | | write_cxxrtl: add support for hierarchical designs.whitequark2020-04-091-18/+107
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Hierarchical design simulations are generally much slower, but this comes with a major increase in flexibility: 1. Since the `flatten` pass currently does not support flattening of designs with processes, this is the only way to simulate such designs with cxxrtl. 2. Support for hierarchy paves way for simulation black boxes, which are necessary for e.g. replacing PHYs with C++ code that integrates with the host system.
| * | | write_cxxrtl: avoid undefined behavior on out-of-bounds memory access.whitequark2020-04-092-46/+78
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | After this commit, if NDEBUG is not defined, out-of-bounds accesses cause assertion failures for reads and writes. If NDEBUG is defined, out-of-bounds reads return zeroes, and out-of-bounds writes are ignored. This commit also adds support for memories that start with a non-zero index (`Memory::start_offset` in RTLIL).
| * | | write_cxxrtl: statically schedule comb logic and localize wires.whitequark2020-04-092-68/+368
| | | | | | | | | | | | | | | | | | | | | | | | This results in further massive gains in performance, modest decrease in compile time, and, for designs without feedback arcs, makes it possible to run eval() once per clock edge in certain conditions.
| * | | write_cxxrtl: elide wires for results of comb cells used once.whitequark2020-04-091-35/+359
| | | | | | | | | | | | | | | | | | | | This results in massive gains in performance, equally massive reduction in compile time, and improved readability.
| * | | write_cxxrtl: new backend.whitequark2020-04-096-0/+2016
| | | | | | | | | | | | | | | | | | | | This commit adds a basic implementation that isn't very performant but implements most of the planned features.
* | | | Merge pull request #1858 from YosysHQ/eddie/fix1856Eddie Hung2020-04-096-3/+25
|\ \ \ \ | | | | | | | | | | kernel: include "kernel/constids.inc"
| * | | | tests: add a quick plugin testEddie Hung2020-04-093-0/+22
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| * | | | kernel: include "kernel/constids.inc" instead of "constids.inc"Eddie Hung2020-04-093-3/+3
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