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* Add skeleton for new BTOR back-endClifford Wolf2017-11-232-0/+216
* Remove old BTOR back-endClifford Wolf2017-11-234-1174/+0
* Accept real-valued delay valuesClifford Wolf2017-11-181-0/+1
* Merge pull request #452 from cr1901/masterClifford Wolf2017-11-181-4/+20
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| * Accommodate Windows-style paths during include-file processing.William D. Jones2017-11-141-4/+20
* | Merge pull request #453 from dh73/masterClifford Wolf2017-11-1814-9/+316
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| * | Fixed the -vout flag to -vqm in examples/intel directorydh732017-11-144-4/+4
| * | Initial Cyclone 10 supportdh732017-11-085-1/+308
| * | Merge https://github.com/cliffordwolf/yosysdh732017-11-0825-449/+588
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| * | Organizing Speedster file namesdh732017-11-085-4/+4
* | | Add "synth_ice40 -vpr"Clifford Wolf2017-11-162-5/+29
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* | Add support for editline as replacement for readlineClifford Wolf2017-11-084-10/+39
* | Add "ltp" commandClifford Wolf2017-10-312-0/+186
* | Fix SMT2 handling of initstate in sub-modulesClifford Wolf2017-10-291-0/+3
* | Fix memory corruption bug in opt_rmdffClifford Wolf2017-10-261-0/+3
* | Fix typo in opt_clean log messageClifford Wolf2017-10-261-1/+1
* | Improve smtio performance by using reader thread, not writer threadClifford Wolf2017-10-261-10/+30
* | Use separate writer thread for talking to SMT solver to avoid read/write dead...Clifford Wolf2017-10-251-8/+23
* | Improve p_* functions in smtio.pyClifford Wolf2017-10-251-21/+19
* | Disable OSX in .travis.ymlClifford Wolf2017-10-251-2/+2
* | Add ENABLE_DEBUG config flagClifford Wolf2017-10-251-1/+10
* | Update ABC to hg rev f6838749f234Clifford Wolf2017-10-251-1/+1
* | Remove vhdl2verilogClifford Wolf2017-10-252-184/+0
* | Capsulate smt-solver read/write in separate functionsClifford Wolf2017-10-251-8/+24
* | Fix a bug in yosys-smtbmc in ROM handlingClifford Wolf2017-10-251-0/+3
* | Remove PSL example from tests/sva/Clifford Wolf2017-10-202-35/+1
* | Remove all PSL support code from verific.ccClifford Wolf2017-10-201-179/+17
* | Merge pull request #437 from mithro/masterClifford Wolf2017-10-202-1/+14
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| * | Adding COPYING file with license information.Tim 'mithro' Ansell2017-10-192-1/+14
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* | Revert 90be0d8 as it causes endless loops for some designsClifford Wolf2017-10-141-1/+0
* | Add "verific -vlog-libdir"Clifford Wolf2017-10-131-0/+12
* | Add "verific -vlog-incdir" and "verific -vlog-define"Clifford Wolf2017-10-131-0/+35
* | Update Verific READMEClifford Wolf2017-10-131-0/+7
* | Merge pull request #434 from Kmanfi/vector_fixClifford Wolf2017-10-121-0/+1
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| * | Fix input vector for reduce cells.Kaj Tuomi2017-10-121-0/+1
* | | Add Verific fairness/liveness supportClifford Wolf2017-10-121-11/+32
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* | Update ABC to hg rev 6283c5d99b06Clifford Wolf2017-10-111-1/+1
* | Merge branch 'master' of github.com:cliffordwolf/yosysClifford Wolf2017-10-1028-211/+234
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| * | Rewrite ABC output to include proper net names in timing reportClifford Wolf2017-10-101-2/+17
| * | Add timing constraints to osu035 exampleClifford Wolf2017-10-103-2/+4
| * | Remove some dead codeClifford Wolf2017-10-101-15/+0
| * | Allow $past, $stable, $rose, $fell in $global_clock blocksClifford Wolf2017-10-101-1/+5
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| * Add $shiftx support to verilog front-endClifford Wolf2017-10-071-0/+17
| * Update ABC to hg rev 0fc1803a77c0Clifford Wolf2017-10-061-1/+1
| * Clean whitespace and permissions in techlibs/intelLarry Doolittle2017-10-0521-190/+190
* | Start work on pre-processor for Verific SVA propertiesClifford Wolf2017-10-101-10/+153
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* Improve handling of Verific errorsClifford Wolf2017-10-051-11/+9
* Improve Verific error handling, check VHDL static assertsClifford Wolf2017-10-041-11/+25
* Add blackbox commandClifford Wolf2017-10-042-0/+82
* Fix nasty bug in Verific bindingsClifford Wolf2017-10-041-1/+1
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