| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| | | * | | improve clkbuf_inhibit propagation upwards through hierarchy | Marcin Kościelnicki | 2019-08-27 | 2 | -6/+45 | |
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| | | * | | Improve tests to check that clkbuf is connected to expected | Eddie Hung | 2019-08-26 | 1 | -6/+21 | |
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| | | * | | Merge branch 'master' into mwk/xilinx_bufgmap | Eddie Hung | 2019-08-26 | 8 | -60/+405 | |
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| | | * \ \ | Merge branch 'master' into mwk/xilinx_bufgmap | Eddie Hung | 2019-08-23 | 1 | -1/+1 | |
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| | | * \ \ \ | Merge branch 'master' into mwk/xilinx_bufgmap | Eddie Hung | 2019-08-23 | 3 | -18/+36 | |
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| | | * | | | | | Check clkbuf_inhibit=1 is ignored for custom selection | Eddie Hung | 2019-08-23 | 1 | -0/+1 | |
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| | | * | | | | | clkbufmap to only check clkbuf_inhibit if no selection given | Eddie Hung | 2019-08-23 | 1 | -5/+18 | |
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| | | * | | | | | Add simple clkbufmap tests | Eddie Hung | 2019-08-23 | 1 | -0/+52 | |
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| | | * | | | | | tests/techmap/run-test.sh to cope with *.ys | Eddie Hung | 2019-08-23 | 2 | -7/+18 | |
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| | | * | | | | | Mention clkbuf_inhibit can be overridden | Eddie Hung | 2019-08-23 | 1 | -7/+8 | |
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| | | * | | | | | Review comment from @cliffordwolf | Eddie Hung | 2019-08-23 | 1 | -1/+2 | |
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| | | * | | | | | Merge remote-tracking branch 'origin/master' into mwk/xilinx_bufgmap | Eddie Hung | 2019-08-23 | 146 | -1486/+4373 | |
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| | | * \ \ \ \ \ | Merge remote-tracking branch 'origin/master' into mwk/xilinx_bufgmap | Eddie Hung | 2019-08-16 | 57 | -3403/+3432 | |
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| | | * | | | | | | | README updates | Marcin Kościelnicki | 2019-08-13 | 1 | -0/+14 | |
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| | | * | | | | | | | move attributes to wires | Marcin Kościelnicki | 2019-08-13 | 8 | -311/+546 | |
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| | | * | | | | | | | minor review fixes | Marcin Kościelnicki | 2019-08-13 | 2 | -3/+5 | |
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| | | * | | | | | | | review fixes | Marcin Kościelnicki | 2019-08-13 | 4 | -47/+34 | |
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| | | * | | | | | | | Add clock buffer insertion pass, improve iopadmap. | Marcin Kościelnicki | 2019-08-13 | 10 | -93/+577 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A few new attributes are defined for use in cell libraries: - iopad_external_pin: marks PAD cell's external-facing pin. Pad insertion will be skipped for ports that are already connected to such a pin. - clkbuf_sink: marks an input pin as a clock pin, requesting clock buffer insertion. - clkbuf_driver: marks an output pin as a clock buffer output pin. Clock buffer insertion will be skipped for nets that are already driven by such a pin. All three are module attributes that should be set to a comma-separeted list of pin names. Clock buffer insertion itself works as follows: 1. All cell ports, starting from bottom up, can be marked as clock sinks (requesting clock buffer insertion) or as clock buffer outputs. 2. If a wire in a given module is driven by a cell port that is a clock buffer output, it is in turn also considered a clock buffer output. 3. If an input port in a non-top module is connected to a clock sink in a contained cell, it is also in turn considered a clock sink. 4. If a wire in a module is driven by a non-clock-buffer cell, and is also connected to a clock sink port in a contained cell, a clock buffer is inserted in this module. 5. For the top module, a clock buffer is also inserted on input ports connected to clock sinks, optionally with a special kind of input PAD (such as IBUFG for Xilinx). 6. Clock buffer insertion on a given wire is skipped if the clkbuf_inhibit attribute is set on it. | |||||
| | * | | | | | | | | Add "make bumpversion" | Clifford Wolf | 2019-08-27 | 2 | -0/+4 | |
| | | |_|_|_|_|/ / | |/| | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | | | | | | | Missing close bracket | Eddie Hung | 2019-08-26 | 1 | -1/+1 | |
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| * | | | | | | | | Revert "In sat: 'x' in init attr should not override constant" | Eddie Hung | 2019-08-26 | 3 | -7/+1 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 2b37a093e95036b267481b2dae2046278eef4040. | |||||
| * | | | | | | | | Remove leftover header | Eddie Hung | 2019-08-26 | 1 | -1/+0 | |
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| * | | | | | | | | Improve xilinx_srl.fixed generate, add .variable generate | Eddie Hung | 2019-08-26 | 1 | -26/+75 | |
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| * | | | | | | | | Account for maxsubcnt overflowing | Eddie Hung | 2019-08-26 | 1 | -1/+1 | |
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| * | | | | | | | | Add xilinx_srl_pm.variable to test_pmgen | Eddie Hung | 2019-08-26 | 1 | -0/+2 | |
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| * | | | | | | | | Populate generate for xilinx_srl.fixed pattern | Eddie Hung | 2019-08-26 | 1 | -22/+54 | |
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| * | | | | | | | | Add xilinx_srl_fixed, fix typos | Eddie Hung | 2019-08-26 | 1 | -2/+6 | |
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| * | | | | | | | | Merge branch 'master' into eddie/xilinx_srl | Eddie Hung | 2019-08-26 | 4 | -28/+125 | |
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| | * | | | | | | | Remove dupe in CHANGELOG, missing end quote | Eddie Hung | 2019-08-26 | 1 | -2/+1 | |
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| | * | | | | | | | Merge tag 'yosys-0.9' | Clifford Wolf | 2019-08-26 | 2 | -11/+107 | |
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| | | * | | | | | | | Yosys 0.9 | Clifford Wolf | 2019-08-26 | 1 | -1/+1 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | | * | | | | | | | Revert earliest to gcc-4.8, compile iverilog with default compiler | Eddie Hung | 2019-08-23 | 2 | -3/+3 | |
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| | | * | | | | | | | Revert "Bump to gcc-5 as `__warn_memset_zero_len' symbol not in 16.04!?!" | Eddie Hung | 2019-08-23 | 1 | -5/+3 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit c82b2fa31f8965be2680c87af6cd9ac5d26ead4d. | |||||
| | | * | | | | | | | Remove .0 from clang-8.0 | Eddie Hung | 2019-08-23 | 1 | -2/+2 | |
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| | | * | | | | | | | Bump to gcc-5 as `__warn_memset_zero_len' symbol not in 16.04!?! | Eddie Hung | 2019-08-23 | 1 | -3/+5 | |
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| | | * | | | | | | | bionic -> xenial as its on whitelist | Eddie Hung | 2019-08-23 | 1 | -1/+1 | |
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| | | * | | | | | | | Bump gcc from 4.8 to 4.9 as undefined reference | Eddie Hung | 2019-08-23 | 1 | -35/+7 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ... to `__warn_memset_zero_len'. Also remove gcc-6, bump gcc-7 to gcc-9, clang from 5.0 to 8.0 | |||||
| | | * | | | | | | | Make macOS depenency clear | Miodrag Milanovic | 2019-08-23 | 1 | -2/+5 | |
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| | | * | | | | | | | do not require boost if pyosys is not used | Miodrag Milanovic | 2019-08-22 | 1 | -0/+2 | |
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| | | * | | | | | | | require tcl-tk in Brewfile | Chris Shucksmith | 2019-08-22 | 1 | -0/+1 | |
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| | | * | | | | | | | Bump year in copyright notice | Clifford Wolf | 2019-08-22 | 3 | -3/+3 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | | * | | | | | | | Visual Studio build fix | Miodrag Milanovic | 2019-08-02 | 1 | -0/+1 | |
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| | | * | | | | | | | Fix linking issue for new mxe and pthread | Miodrag Milanovic | 2019-08-02 | 1 | -1/+2 | |
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| | | * | | | | | | | Fix yosys linking for mxe | Miodrag Milanovic | 2019-08-02 | 1 | -1/+1 | |
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| | | * | | | | | | | New mxe hacks needed to support 2ca237e | Miodrag Milanovic | 2019-08-02 | 1 | -0/+4 | |
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| | | * | | | | | | | Fix formatting for msys2 mingw build using GetSize | Miodrag Milanovic | 2019-08-02 | 8 | -17/+20 | |
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| | | * | | | | | | | Update CHANGELOG | David Shah | 2019-07-26 | 1 | -10/+101 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
| | | * | | | | | | | Merge pull request #1175 from whitequark/write_verilog-fix-case-attr-position | Clifford Wolf | 2019-07-09 | 1 | -3/+2 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | write_verilog: fix placement of case attributes | |||||
| | | * | | | | | | | Update CHANGELOG | David Shah | 2019-07-09 | 1 | -0/+1 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
| | | * | | | | | | | Merge pull request #1163 from whitequark/more-case-attrs | Clifford Wolf | 2019-07-09 | 3 | -16/+28 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | More support for case rule attributes | |||||
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index : iCE40/yosys | |
| clone of https://github.com/YosysHQ/yosys |
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