| Commit message (Expand) | Author | Age | Files | Lines |
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| | | * | | | | | | | | | | | | | Really permute Xilinx LUT mappings as default LUT6.I5:A6 | Eddie Hung | 2019-06-18 | 1 | -16/+16 |
| | | * | | | | | | | | | | | | | Revert "Fix (do not) permute LUT inputs, but permute mux selects" | Eddie Hung | 2019-06-18 | 1 | -33/+31 |
| | | * | | | | | | | | | | | | | Clean up | Eddie Hung | 2019-06-18 | 1 | -6/+4 |
| | | * | | | | | | | | | | | | | Fix (do not) permute LUT inputs, but permute mux selects | Eddie Hung | 2019-06-18 | 1 | -31/+33 |
| | | * | | | | | | | | | | | | | Fix copy-pasta issue | Eddie Hung | 2019-06-17 | 1 | -9/+8 |
| | | * | | | | | | | | | | | | | Permute INIT for +/xilinx/lut_map.v | Eddie Hung | 2019-06-17 | 1 | -32/+58 |
| | | * | | | | | | | | | | | | | Simplify comment | Eddie Hung | 2019-06-17 | 1 | -1/+1 |
| | * | | | | | | | | | | | | | | Merge pull request #1146 from gsomlo/gls-test-abc-ext | Clifford Wolf | 2019-06-28 | 4 | -8/+29 |
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| | | * | | | | | | | | | | | | | | tests: use optional ABCEXTERNAL when specified | Gabriel L. Somlo | 2019-06-27 | 4 | -8/+29 |
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| | * | | | | | | | | | | | | | | Merge pull request #1046 from bogdanvuk/master | Clifford Wolf | 2019-06-28 | 5 | -16/+127 |
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| | | * | | | | | | | | | | | | | Add help for "-sat" option inside opt_rmdff. "opt" can pass "-sat" too | Bogdan Vukobratovic | 2019-06-27 | 2 | -2/+10 |
| | | * | | | | | | | | | | | | | Fix memory leak when one of multiple DFF cells is removed in opt_rmdff | Bogdan Vukobratovic | 2019-06-27 | 1 | -0/+5 |
| | | * | | | | | | | | | | | | | Merge remote-tracking branch 'upstream/master' | Bogdan Vukobratovic | 2019-06-27 | 37 | -143/+1631 |
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| | | * | | | | | | | | | | | | | | Refactor "opt_rmdff -sat" | Clifford Wolf | 2019-06-20 | 4 | -373/+58 |
| | | * | | | | | | | | | | | | | | Merge branch 'master' of https://github.com/bogdanvuk/yosys into clifford/ext... | Clifford Wolf | 2019-06-20 | 5 | -10/+423 |
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| | | | * | | | | | | | | | | | | | | Move netlist helper module to passes/opt for the time being | Bogdan Vukobratovic | 2019-06-14 | 2 | -1/+1 |
| | | | * | | | | | | | | | | | | | | Merge remote-tracking branch 'upstream/master' | Bogdan Vukobratovic | 2019-06-14 | 73 | -475/+1352 |
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| | | | * | | | | | | | | | | | | | | | Prepare for situation when port of the signal cannot be found | Bogdan Vukobratovic | 2019-06-14 | 2 | -2/+8 |
| | | | * | | | | | | | | | | | | | | | Some cleanup, revert sat.cc | Bogdan Vukobratovic | 2019-06-14 | 2 | -13/+11 |
| | | | * | | | | | | | | | | | | | | | Implement disconnection of constant register bits | Bogdan Vukobratovic | 2019-06-13 | 2 | -44/+109 |
| | | | * | | | | | | | | | | | | | | | Pass SigBit by value to Netlist algorithms | Bogdan Vukobratovic | 2019-06-13 | 1 | -65/+84 |
| | | | * | | | | | | | | | | | | | | | Rename satgen_algo.h -> algo.h, code cleanup and refactoring | Bogdan Vukobratovic | 2019-06-12 | 4 | -279/+265 |
| | | | * | | | | | | | | | | | | | | | Generate satgen instance instead of calling sat pass | Bogdan Vukobratovic | 2019-06-11 | 2 | -24/+129 |
| | | | * | | | | | | | | | | | | | | | Refactor driver map generation | Bogdan Vukobratovic | 2019-06-10 | 1 | -0/+158 |
| | | | * | | | | | | | | | | | | | | | Fix the regression | Bogdan Vukobratovic | 2019-05-28 | 1 | -1/+2 |
| | | | * | | | | | | | | | | | | | | | Merge remote-tracking branch 'upstream/master' | Bogdan Vukobratovic | 2019-05-28 | 1 | -1/+11 |
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| | | | * | | | | | | | | | | | | | | | | Optimizing DFFs whose initial value prevents their value from changing | Bogdan Vukobratovic | 2019-05-28 | 4 | -3/+78 |
| | * | | | | | | | | | | | | | | | | | | Merge pull request #1139 from YosysHQ/dave/check-sim-iverilog | Eddie Hung | 2019-06-27 | 2 | -0/+19 |
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| | | * | | | | | | | | | | | | | | | | | Add simcells.v, simlib.v, and some output | Eddie Hung | 2019-06-27 | 1 | -1/+11 |
| | | * | | | | | | | | | | | | | | | | | tests: Check that Icarus can parse arch sim models | David Shah | 2019-06-26 | 2 | -0/+9 |
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| | * | | | | | | | | | | | | | | | | | Grr | Eddie Hung | 2019-06-27 | 1 | -1/+1 |
| | * | | | | | | | | | | | | | | | | | Capitalisation | Eddie Hung | 2019-06-27 | 1 | -1/+1 |
| | * | | | | | | | | | | | | | | | | | Make CHANGELOG clearer | Eddie Hung | 2019-06-27 | 1 | -0/+1 |
| | * | | | | | | | | | | | | | | | | | Merge pull request #1143 from YosysHQ/clifford/fix1135 | Eddie Hung | 2019-06-27 | 4 | -8/+38 |
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| | | * | | | | | | | | | | | | | | | | Add #1135 testcase | Eddie Hung | 2019-06-27 | 2 | -5/+26 |
| | | * | | | | | | | | | | | | | | | | Add "pmux2shiftx -norange", fixes #1135 | Clifford Wolf | 2019-06-27 | 2 | -3/+12 |
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| | * | | | | | | | | | | | | | | | | synth_xilinx -arch -> -family, consistent with older synth_intel | Eddie Hung | 2019-06-27 | 1 | -7/+8 |
| | * | | | | | | | | | | | | | | | | Merge pull request #1142 from YosysHQ/clifford/fix1132 | Eddie Hung | 2019-06-27 | 2 | -6/+345 |
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| | | * | | | | | | | | | | | | | | | | Copy tests from eddie/fix1132 | Eddie Hung | 2019-06-27 | 1 | -0/+320 |
| | | * | | | | | | | | | | | | | | | | Fix handling of partial covers in muxcover, fixes #1132 | Clifford Wolf | 2019-06-27 | 1 | -6/+25 |
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| | * | | | | | | | | | | | | | | | | Merge pull request #1138 from YosysHQ/koriakin/xc7nocarrymux | Eddie Hung | 2019-06-27 | 2 | -12/+34 |
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| | | * | | | | | | | | | | | | | | Grrr | Eddie Hung | 2019-06-26 | 1 | -2/+2 |
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| | | * | | | | | | | | | | | | | Fix spacing | Eddie Hung | 2019-06-26 | 1 | -5/+5 |
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| | | * | | | | | | | | | | | | Oops. Actually use nocarry flag as spotted by @koriakin | Eddie Hung | 2019-06-26 | 1 | -5/+7 |
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| | | * | | | | | | | | | | | synth_ecp5 rename -nomux to -nowidelut, but preserve former | Eddie Hung | 2019-06-26 | 1 | -6/+6 |
| | | * | | | | | | | | | | | Merge branch 'xc7nocarrymux' of https://github.com/koriakin/yosys into koriak... | Eddie Hung | 2019-06-26 | 1 | -4/+24 |
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| | | | * | | | | | | | | | | synth_xilinx: Add -nocarry and -nomux options. | Marcin Kościelnicki | 2019-04-30 | 1 | -7/+26 |
| | * | | | | | | | | | | | | Merge pull request #1137 from mmicko/cell_sim_fix | Clifford Wolf | 2019-06-26 | 2 | -14/+1 |
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| | | * | | | | | | | | | | | | Simulation model verilog fix | Miodrag Milanovic | 2019-06-26 | 2 | -14/+1 |
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| | * | | | | | | | | | | | | Improve opt_clean handling of unused public wires | Clifford Wolf | 2019-06-26 | 1 | -2/+2 |
