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* Merge branch 'master' into xc7dspDavid Shah2019-08-30190-4390/+8848
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| * Merge pull request #1337 from YosysHQ/eddie/fix_carry_wrapperEddie Hung2019-08-297-27/+71
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| | * Rename boxes tooEddie Hung2019-08-293-3/+3
| | * Add run-test.sh tooEddie Hung2019-08-281-0/+20
| | * Do not overwrite LUT paramEddie Hung2019-08-281-1/+0
| | * Add SB_CARRY to ice40_opt testEddie Hung2019-08-281-3/+5
| | * Add ice40_opt testEddie Hung2019-08-281-0/+24
| | * Trailing commaEddie Hung2019-08-281-1/+1
| | * Adapt to $__ICE40_CARRY_WRAPPEREddie Hung2019-08-281-3/+5
| | * Revert "Remove $__ICE40_FULL_ADDER handling from ice40_opt; cannot reason with"Eddie Hung2019-08-281-0/+45
| | * Remove $__ICE40_FULL_ADDER handling from ice40_opt; cannot reason withEddie Hung2019-08-281-45/+0
| | * Update box size and timingsEddie Hung2019-08-283-12/+12
| | * Update to new $__ICE40_CARRY_WRAPPEREddie Hung2019-08-281-11/+8
| * | Fix typo that's gone unnoticed for 5 months!?!Eddie Hung2019-08-291-1/+1
| * | Bump YOSYS_VERClifford Wolf2019-08-291-1/+1
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| * Merge pull request #1334 from YosysHQ/clifford/async2synclatchEddie Hung2019-08-281-1/+36
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| | * Add $dlatch support to async2syncClifford Wolf2019-08-281-1/+36
| * | Add (* clkbuf_sink *) to SRLC16E, reorder ports to match vendorEddie Hung2019-08-281-3/+8
| * | Merge pull request #1332 from YosysHQ/dave/ecp5gsrDavid Shah2019-08-286-54/+212
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| | * | ecp5: Add GSR supportDavid Shah2019-08-276-54/+212
| * | | Merge pull request #1335 from YosysHQ/clifford/paramapClifford Wolf2019-08-281-68/+119
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| | * | Fix typoClifford Wolf2019-08-281-2/+2
| | * | Add "paramap" passClifford Wolf2019-08-281-67/+118
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| * | Merge pull request #1325 from YosysHQ/eddie/sat_initClifford Wolf2019-08-282-2/+8
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| | * | Ignore all 1'bx in (* init *)Eddie Hung2019-08-271-3/+1
| | * | Revert to using cleanEddie Hung2019-08-271-1/+1
| | * | Wire with init on FF part, 1'bx on non-FF partEddie Hung2019-08-241-1/+3
| | * | Blocking assignmentEddie Hung2019-08-231-1/+1
| | * | In sat: 'x' in init attr should not override constantEddie Hung2019-08-223-1/+7
| * | | xilinx: Add SRLC16E primitive.Marcin Kościelnicki2019-08-271-1/+21
| * | | Merge pull request #1292 from YosysHQ/mwk/xilinx_bufgmapEddie Hung2019-08-2716-223/+1075
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| | * | improve clkbuf_inhibit propagation upwards through hierarchyMarcin Kościelnicki2019-08-272-6/+45
| | * | Improve tests to check that clkbuf is connected to expectedEddie Hung2019-08-261-6/+21
| | * | Merge branch 'master' into mwk/xilinx_bufgmapEddie Hung2019-08-268-60/+405
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| | * \ \ Merge branch 'master' into mwk/xilinx_bufgmapEddie Hung2019-08-231-1/+1
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| | * \ \ \ Merge branch 'master' into mwk/xilinx_bufgmapEddie Hung2019-08-233-18/+36
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| | * | | | | Check clkbuf_inhibit=1 is ignored for custom selectionEddie Hung2019-08-231-0/+1
| | * | | | | clkbufmap to only check clkbuf_inhibit if no selection givenEddie Hung2019-08-231-5/+18
| | * | | | | Add simple clkbufmap testsEddie Hung2019-08-231-0/+52
| | * | | | | tests/techmap/run-test.sh to cope with *.ysEddie Hung2019-08-232-7/+18
| | * | | | | Mention clkbuf_inhibit can be overriddenEddie Hung2019-08-231-7/+8
| | * | | | | Review comment from @cliffordwolfEddie Hung2019-08-231-1/+2
| | * | | | | Merge remote-tracking branch 'origin/master' into mwk/xilinx_bufgmapEddie Hung2019-08-23146-1486/+4373
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| | * \ \ \ \ \ Merge remote-tracking branch 'origin/master' into mwk/xilinx_bufgmapEddie Hung2019-08-1657-3403/+3432
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| | * | | | | | | README updatesMarcin Kościelnicki2019-08-131-0/+14
| | * | | | | | | move attributes to wiresMarcin Kościelnicki2019-08-138-311/+546
| | * | | | | | | minor review fixesMarcin Kościelnicki2019-08-132-3/+5
| | * | | | | | | review fixesMarcin Kościelnicki2019-08-134-47/+34
| | * | | | | | | Add clock buffer insertion pass, improve iopadmap.Marcin Kościelnicki2019-08-1310-93/+577
| * | | | | | | | Add "make bumpversion"Clifford Wolf2019-08-272-0/+4
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