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* Remove Xilinx testEddie Hung2019-08-221-34/+0
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* Actually, there might not be any harm in updating sigmap...Eddie Hung2019-08-221-3/+1
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* Add comment as per @cliffordwolfEddie Hung2019-08-221-0/+11
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* Add shregmap -tech xilinx testEddie Hung2019-08-221-0/+1
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* Revert "Try way that doesn't involve creating a new wire"Eddie Hung2019-08-221-15/+10
| | | | This reverts commit 2f427acc9ed23c77e89386f4fbf53ac580bf0f0b.
* Try way that doesn't involve creating a new wireEddie Hung2019-08-221-10/+15
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* If d_bit already in sigbit_chain_next, create extra wireEddie Hung2019-08-221-3/+6
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* Add docEddie Hung2019-08-221-1/+14
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* Add copyrightEddie Hung2019-08-221-0/+1
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* Add CHANGELOG entryEddie Hung2019-08-221-0/+2
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* Remove `shregmap -tech xilinx` additionsEddie Hung2019-08-221-189/+8
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* pmgen to also iterate over all module portsEddie Hung2019-08-221-2/+4
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* Remove output_bitsEddie Hung2019-08-222-16/+7
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* Forgot to set ud_variable.minlenEddie Hung2019-08-221-0/+1
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* Do not run xilinx_srl_pm in fixed loopEddie Hung2019-08-221-28/+24
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* Merge remote-tracking branch 'origin/master' into eddie/xilinx_srlEddie Hung2019-08-2219-102/+1046
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| * Merge pull request #1317 from YosysHQ/eddie/opt_expr_shiftxEddie Hung2019-08-222-4/+96
| |\ | | | | | | opt_expr to trim A port of $shiftx/$shift
| | * Copy-paste typoEddie Hung2019-08-221-1/+1
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| | * Respect opt_expr -keepdc as per @cliffordwolfEddie Hung2019-08-222-1/+15
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| | * Handle $shift and Y_WIDTH > 1 as per @cliffordwolfEddie Hung2019-08-222-5/+51
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| | * Add cover()Eddie Hung2019-08-221-0/+1
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| | * Canonical formEddie Hung2019-08-221-5/+5
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| | * Add testEddie Hung2019-08-211-0/+14
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| | * opt_expr to trim A port of $shiftx if Y_WIDTH == 1Eddie Hung2019-08-211-0/+17
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| * | Bump year in copyright noticeClifford Wolf2019-08-223-3/+3
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Fix missing newline at end of fileClifford Wolf2019-08-221-1/+1
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Merge pull request #1289 from mmicko/anlogic_fixesClifford Wolf2019-08-225-91/+162
| |\ \ | | | | | | | | Anlogic fixes and optimization
| | * \ Merge remote-tracking branch 'upstream/master' into anlogic_fixesMiodrag Milanovic2019-08-18109-3621/+4745
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| | * | | Proper arith for Anlogic and use standard passMiodrag Milanovic2019-08-125-91/+162
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| * | | | Fix missing newline at end of fileClifford Wolf2019-08-221-1/+1
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | | Merge pull request #1281 from mmicko/efinixClifford Wolf2019-08-229-0/+798
| |\ \ \ \ | | | | | | | | | | | | Initial support for Efinix Trion series FPGAs
| | * | | | Fix formatingMiodrag Milanovic2019-08-111-2/+2
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| | * | | | one bit enable signalMiodrag Milanovic2019-08-111-1/+1
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| | * | | | fix mixing signals on FF mappingMiodrag Milanovic2019-08-111-4/+4
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| | * | | | Replaced custom step with setundefMiodrag Milanovic2019-08-113-91/+1
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| | * | | | Fixed data widthMiodrag Milanovic2019-08-111-2/+2
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| | * | | | Adding new pass to fix carry chainMiodrag Milanovic2019-08-113-0/+124
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| | * | | | cleanupMiodrag Milanovic2019-08-111-4/+7
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| | * | | | Fix COMiodrag Milanovic2019-08-091-26/+24
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| | * | | | Merge remote-tracking branch 'upstream/master' into efinixMiodrag Milanovic2019-08-0958-598/+1321
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| | * | | | | clock for ram trough gbufMiodrag Milanovic2019-08-041-0/+6
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| | * | | | | Added bram supportMiodrag Milanovic2019-08-046-1/+260
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| | * | | | | Custom step to add global clock buffersMiodrag Milanovic2019-08-034-1/+129
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| | * | | | | Initial EFINIX supportMiodrag Milanovic2019-08-035-0/+370
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* | | | | | | Merge remote-tracking branch 'origin/master' into eddie/xilinx_srlEddie Hung2019-08-221-1/+1
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| * | | | | | Merge pull request #1316 from YosysHQ/eddie/fix_mem2regClifford Wolf2019-08-222-0/+17
| |\ \ \ \ \ \ | | | | | | | | | | | | | | | | mem2reg to preserve user attributes and src
| * \ \ \ \ \ \ Merge pull request #1315 from mmicko/fix_dependencieswhitequark2019-08-211-1/+1
| |\ \ \ \ \ \ \ | | |_|_|_|_|_|/ | |/| | | | | | Fix test_pmgen deps
| | * | | | | | Fix test_pmgen depsMiodrag Milanovic2019-08-211-1/+1
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* | | | | | | Reuse varEddie Hung2019-08-211-1/+1
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* | | | | | | Revert "Trim shiftx_width when upper bits are 1'bx"Eddie Hung2019-08-211-6/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 7e7965ca7b3bbeb79cb70014da7bc48c08a74adb.
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