| Commit message (Expand) | Author | Age | Files | Lines | ||
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| | * | | | synth_ice40: add -noabc option, to use built-in LUT techmapping. | whitequark | 2018-12-05 | 1 | -2/+16 | |
| | * | | | gate2lut: new techlib, for converting Yosys gates to FPGA LUTs. | whitequark | 2018-12-05 | 10 | -0/+133 | |
| | * | | | Fix typo. | whitequark | 2018-12-05 | 1 | -2/+2 | |
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| * | | | Merge pull request #713 from Diego-HR/master | Clifford Wolf | 2018-12-05 | 5 | -12/+91 | |
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| | * | | | Changes in GoWin synth commands and ALU primitive support | Diego H | 2018-12-03 | 5 | -12/+91 | |
| * | | | | Merge pull request #712 from mmicko/anlogic-support | Clifford Wolf | 2018-12-05 | 7 | -0/+1278 | |
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| | * | | | | Leave only real black box cells | Miodrag Milanovic | 2018-12-02 | 1 | -312/+0 | |
| | * | | | | Initial support for Anlogic FPGA | Miodrag Milanovic | 2018-12-01 | 7 | -0/+1590 | |
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| * | | | | Rename opt_lut.cpp to opt_lut.cc | Clifford Wolf | 2018-12-05 | 1 | -0/+0 | |
| * | | | | Merge pull request #717 from whitequark/opt_lut | Clifford Wolf | 2018-12-05 | 9 | -2/+537 | |
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| | * | | | | opt_lut: add -dlogic, to avoid disturbing logic such as carry chains. | whitequark | 2018-12-05 | 3 | -20/+166 | |
| | * | | | | opt_lut: always prefer to eliminate 1-LUTs. | whitequark | 2018-12-05 | 1 | -19/+41 | |
| | * | | | | opt_lut: collect and display statistics. | whitequark | 2018-12-05 | 1 | -4/+33 | |
| | * | | | | opt_lut: refactor to use a worker. NFC. | whitequark | 2018-12-05 | 1 | -170/+177 | |
| | * | | | | synth_ice40: add -relut option, to run ice40_unlut and opt_lut. | whitequark | 2018-12-05 | 1 | -1/+13 | |
| | * | | | | opt_lut: new pass, to combine LUTs for tighter packing. | whitequark | 2018-12-05 | 8 | -1/+320 | |
| * | | | | | Merge pull request #716 from whitequark/ice40_unlut | Clifford Wolf | 2018-12-05 | 3 | -13/+109 | |
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| | * | | | | Extract ice40_unlut pass from ice40_opt. | whitequark | 2018-12-05 | 3 | -13/+109 | |
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| * | | | | Merge pull request #719 from YosysHQ/q3k/flailing-around-trying-to-fix-osx | Serge Bazanski | 2018-12-05 | 2 | -3/+2 | |
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| | * | | | | travis/osx: fix, use clang instead of gcc | Sergiusz Bazanski | 2018-12-05 | 2 | -3/+2 | |
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| * | | | | Fix typo | Clifford Wolf | 2018-12-04 | 1 | -1/+1 | |
| * | | | | Merge pull request #702 from smunaut/min_ce_use | Clifford Wolf | 2018-12-04 | 2 | -1/+50 | |
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| | * | | | ice40: Add option to only use CE if it'd be use by more than X FFs | Sylvain Munaut | 2018-11-27 | 1 | -0/+14 | |
| | * | | | dff2dffe: Add option for unmap to only remove DFFE with low CE signal use | Sylvain Munaut | 2018-11-27 | 1 | -1/+36 | |
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| * | | | Merge pull request #676 from rafaeltp/master | Clifford Wolf | 2018-12-01 | 1 | -10/+17 | |
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| | * | | | using [i] to access individual bits of SigSpec and merging bits into a tmp Si... | rafaeltp | 2018-10-21 | 1 | -11/+12 | |
| | * | | | cleaning up for PR | rafaeltp | 2018-10-20 | 2 | -6/+2 | |
| | * | | | fixing code style | rafaeltp | 2018-10-20 | 1 | -1/+1 | |
| | * | | | solves #675 | rafaeltp | 2018-10-20 | 2 | -11/+21 | |
| | * | | | Merge pull request #1 from YosysHQ/master | rafaeltp | 2018-10-20 | 20 | -89/+869 | |
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| * | | | | | Improve ConstEval error handling for non-eval cell types | Clifford Wolf | 2018-11-29 | 2 | -9/+19 | |
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| * | | | | Add iteration limit to "opt_muxtree" | Clifford Wolf | 2018-11-20 | 1 | -1/+17 | |
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| * | | | Update ABC to git rev 2ddc57d | Clifford Wolf | 2018-11-13 | 1 | -1/+1 | |
| * | | | Add "write_aiger -I -O -B" | Clifford Wolf | 2018-11-12 | 1 | -2/+36 | |
| * | | | Merge branch 'master' of github.com:YosysHQ/yosys | Clifford Wolf | 2018-11-12 | 4 | -1/+1044 | |
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| | * \ \ | Merge pull request #697 from eddiehung/xilinx_ps7 | Clifford Wolf | 2018-11-12 | 2 | -0/+624 | |
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| | | * | | | Add support for Xilinx PS7 block | Eddie Hung | 2018-11-10 | 2 | -0/+624 | |
| | * | | | | Merge pull request #695 from daveshah1/ecp5_bb | Clifford Wolf | 2018-11-12 | 2 | -1/+420 | |
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| | | * | | | ecp5: Add 'fake' DCU parameters | David Shah | 2018-11-09 | 1 | -0/+11 | |
| | | * | | | ecp5: Add blackboxes for ancillary DCU cells | David Shah | 2018-11-09 | 1 | -0/+18 | |
| | | * | | | ecp5: Adding some blackbox cells | David Shah | 2018-11-07 | 2 | -1/+391 | |
| * | | | | | Update ABC to git rev 68da3cf | Clifford Wolf | 2018-11-11 | 1 | -1/+1 | |
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| * | | | | Set Verific flag vhdl_support_variable_slice=1 | Clifford Wolf | 2018-11-09 | 1 | -0/+1 | |
| * | | | | Merge pull request #696 from arjenroodselaar/verific_darwin | Clifford Wolf | 2018-11-09 | 1 | -0/+4 | |
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| | * | | | | Use appropriate static libraries when building with Verific on MacOS | Arjen Roodselaar | 2018-11-07 | 1 | -0/+4 | |
| * | | | | | Fix "make ystests" to use correct Yosys binary | Clifford Wolf | 2018-11-08 | 1 | -1/+1 | |
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| * | | | | Merge pull request #693 from YosysHQ/rlimit | Clifford Wolf | 2018-11-07 | 1 | -8/+11 | |
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| | * | | | | Limit stack size to 16 MB on Darwin | Clifford Wolf | 2018-11-07 | 1 | -1/+4 | |
| | * | | | | Fix for improved smtio.py rlimit code | Clifford Wolf | 2018-11-06 | 1 | -1/+1 | |
| | * | | | | Improve stack rlimit code in smtio.py | Clifford Wolf | 2018-11-06 | 1 | -8/+8 | |
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index : iCE40/yosys | |
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