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* Fix input/output attributes when resolving typedef of wireKamil Rakoczy2021-01-181-0/+3
| | | | Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
* Parse package user type in module port listLukasz Dalek2021-01-181-30/+32
| | | | | Signed-off-by: Lukasz Dalek <ldalek@antmicro.com> Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
* Bump versionYosys Bot2021-01-151-1/+1
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* opt_share: Fix X and CO signal width for shifted $alu in opt_share.Marcelina Kościelnicka2021-01-142-2/+22
| | | | | | These need to be the same length as actual Y, not visible part of Y. Fixes #2538.
* Bump versionYosys Bot2021-01-141-1/+1
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* Merge pull request #2537 from pepijndevos/spiceClaire Xen2021-01-131-7/+15
|\ | | | | Add buffer option to spice backend
| * add buffer option to spice backendPepijn de Vos2021-01-131-7/+15
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* Bump versionYosys Bot2021-01-051-1/+1
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* Merge pull request #2522 from tomverbeure/simlib_typos2whitequark2021-01-041-5/+5
|\ | | | | Fix some trivial typos.
| * Fix some trivial typos.Tom Verbeure2021-01-031-5/+5
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* Bump versionYosys Bot2021-01-021-1/+1
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* Merge pull request #2480 from YosysHQ/dave/nexus-lramwhitequark2021-01-015-1/+227
|\ | | | | nexus: Add LRAM inference
| * nexus: Add LRAM inferenceDavid Shah2020-12-075-1/+227
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | Merge pull request #2512 from umarcor/plugin-errwhitequark2021-01-011-1/+5
|\ \ | | | | | | plugin: enhance no-plugin error
| * | plugin: enhance no-plugin errorumarcor2020-12-291-1/+5
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* | | Merge pull request #2515 from umarcor/fix/ghdlwhitequark2021-01-011-2/+2
|\ \ \ | | | | | | | | makefile: fix GHDL vars, replace GHDL_DIR with GHDL_PREFIX
| * | | makefile: fix GHDL vars, replace GHDL_DIR with GHDL_PREFIXumarcor2020-12-301-2/+2
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* | | | Merge pull request #2518 from zachjs/recursionwhitequark2021-01-014-8/+99
|\ \ \ \ | | | | | | | | | | verilog: improved support for recursive functions
| * | | | verilog: improved support for recursive functionsZachary Snow2020-12-314-8/+99
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* | | | Merge pull request #2517 from zachjs/sv-tf-implied-directionwhitequark2021-01-013-0/+39
|\ \ \ \ | |/ / / |/| | | sv: complete support for implied task/function port directions
| * | | sv: complete support for implied task/function port directionsZachary Snow2020-12-313-0/+39
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* / / Bump versionYosys Bot2020-12-301-1/+1
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* | Merge pull request #2509 from zachjs/issue-2427whitequark2020-12-294-1/+56
|\ \ | | | | | | Fix elaboration of whole memory words used as indices
| * | Fix elaboration of whole memory words used as indicesZachary Snow2020-12-264-1/+56
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* | | Merge pull request #2514 from umarcor/feat/ghdlwhitequark2020-12-291-0/+9
|\ \ \ | | | | | | | | makefile: add support for built-in ghdl-yosys-plugin
| * | | makefile: add support for built-in ghdl-yosys-pluginumarcor2020-12-281-0/+9
| | | | | | | | | | | | | | | | | | | | Co-authored-by: Tristan Gingold <tgingold@free.fr> Co-authored-by: whitequark <whitequark@whitequark.org>
* | | | Bump versionYosys Bot2020-12-291-1/+1
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* | | Merge pull request #2511 from umarcor/feat/msys2-32whitequark2020-12-281-5/+7
|\ \ \ | | | | | | | | Update MSYS2 build system
| * | | makefile: rename msys2 to msys2-32, config PREFIXumarcor2020-12-281-5/+7
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* | | | Merge pull request #2507 from umarcor/fix/msys2whitequark2020-12-281-2/+3
|\| | | | | | | | | | | kernel/yosys.h: undef CONST on WIN32
| * | | kernel/yosys.h: undef CONST on WIN32umarcor2020-12-281-2/+3
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* | | Bump versionYosys Bot2020-12-281-1/+1
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* | | Merge pull request #2510 from YosysHQ/whitequark/CODEOWNERS-verilog-astClaire Xen2020-12-271-0/+3
|\ \ \ | |/ / |/| | CODEOWNERS: add @zachjs as Verilog/AST frontend owner
| * | CODEOWNERS: add @zachjs as Verilog/AST frontend ownerwhitequark2020-12-271-0/+3
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* | Bump versionYosys Bot2020-12-271-1/+1
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* | Merge pull request #2506 from zachjs/const-arg-redeclareMiodrag Milanović2020-12-262-5/+26
|\ \ | | | | | | Fix constants bound to redeclared function args
| * | Fix constants bound to redeclared function argsZachary Snow2020-12-262-5/+26
|/ / | | | | | | | | | | | | | | The changes in #2476 ensured that function inputs like `input x;` retained their single-bit size when instantiated with a constant argument and turned into a localparam. That change did not handle the possibility for an input to be redeclared later on with an explicit width, such as `integer x;`.
* | Bump versionYosys Bot2020-12-241-1/+1
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* | Merge pull request #2502 from ldoolitt/masterwhitequark2020-12-231-2/+2
|\ \ | | | | | | passes/pmgen/pmgen.py: trivial change to remove C++ compiler warnings
| * | passes/pmgen/pmgen.py: trivial change to remove C++ compiler warningsLarry Doolittle2020-12-231-2/+2
| | | | | | | | | | | | Verified that the result still builds and passes self-tests
* | | Merge pull request #2501 from zachjs/genrtlil-tern-signwhitequark2020-12-232-4/+10
|\ \ \ | | | | | | | | genrtlil: fix mux2rtlil generated wire signedness
| * | | genrtlil: fix mux2rtlil generated wire signednessZachary Snow2020-12-222-4/+10
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* | | | Merge pull request #2476 from zachjs/const-arg-widthwhitequark2020-12-232-0/+18
|\ \ \ \ | |_|/ / |/| | | Fix constants bound to single bit arguments (fixes #2383)
| * | | Fix constants bound to single bit arguments (fixes #2383)Zachary Snow2020-12-222-0/+18
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* | | | Bump versionYosys Bot2020-12-231-1/+1
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* | | Merge pull request #2499 from whitequark/cxxrtl-fixeswhitequark2020-12-221-9/+10
|\ \ \ | | | | | | | | cxxrtl: don't crash generating debug information for unused wires
| * | | cxxrtl: don't crash generating debug information for unused wires.whitequark2020-12-221-9/+10
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* | | Merge pull request #2498 from StefanBruens/Fix_opt_lutwhitequark2020-12-221-2/+4
|\ \ \ | | | | | | | | Fix use-after-free in LUT opt pass
| * | | Fix use-after-free in LUT opt passStefanBruens2020-12-221-2/+4
| | | | | | | | | | | | | | | | | | | | RTLIL::Module::remove(Cell* cell) calls `delete cell`. Any subsequent accesses of `cell` then causes undefined behavior.
* | | | Merge pull request #2497 from whitequark/cxxrtl-reflowwhitequark2020-12-222-446/+608
|\ \ \ \ | |/ / / |/| | | cxxrtl: completely rewrite netlist layout code
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