iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
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\| * \| \|	cxxrtl: don't expect user cell inputs to be wires.	whitequark	2021-07-16	1	-2/+2
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* \| \|	Merge pull request #2871 from whitequark/cxxrtl-fix-2540-2841	whitequark	2021-07-16	1	-1/+1
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\| * \| \|	cxxrtl: don't mark buffered internal wires as UNUSED for debug.	whitequark	2021-07-16	1	-1/+1
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* \| \|	Merge pull request #2870 from whitequark/cxxrtl-fix-2739	whitequark	2021-07-16	1	-4/+6
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\| * \| \|	cxxrtl: mark dead local wires as unused even with inlining disabled.	whitequark	2021-07-15	1	-4/+6
* \| \| \|	sv: fix two struct access bugs	Zachary Snow	2021-07-15	5	-1/+102
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* \| \|	Add a test for interfaces on modules loaded on-demand	Rupert Swarbrick	2021-07-14	5	-2/+48
* \| \|	Extract missing module support in hierarchy.cc to a helper function	Rupert Swarbrick	2021-07-14	1	-44/+68
* \| \|	Merge pull request #2866 from rswarbrick/found-init	whitequark	2021-07-14	1	-3/+0
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\| * \| \|	Delete unused found_init variable	Rupert Swarbrick	2021-07-14	1	-3/+0
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* \| \|	kernel/mem: Add a coalesce_inits helper.	Marcelina Kościelnicka	2021-07-13	3	-1/+84
* \| \|	Add support for the Bitwuzla solver	GCHQDeveloper560	2021-07-12	1	-5/+5
* \| \|	kernel/mem: Use delayed removal for inits as well.	Marcelina Kościelnicka	2021-07-12	2	-4/+20
* \| \|	kernel/mem: Add documentation for more helper functions.	Marcelina Kościelnicka	2021-07-12	1	-0/+34
* \| \|	cxxrtl: Support memory writes in processes.	Marcelina Kościelnicka	2021-07-12	1	-6/+55
* \| \|	cxxrtl: Add support for memory read port reset.	Marcelina Kościelnicka	2021-07-12	1	-1/+41
* \| \|	cxxrtl: Add support for mem read port initial data.	Marcelina Kościelnicka	2021-07-12	1	-4/+22
* \| \|	cxxrtl: Convert to Mem helpers.	Marcelina Kościelnicka	2021-07-12	1	-206/+276
* \| \|	kernel/mem: Commit new values of attributes in emit.	Marcelina Kościelnicka	2021-07-12	1	-0/+4
* \| \|	kernel/mem: Make the Mem helpers inherit from AttrObject.	Marcelina Kościelnicka	2021-07-12	1	-8/+4
* \| \|	rtlil: Make Process handling more uniform with Cell and Wire.	Marcelina Kościelnicka	2021-07-12	8	-25/+62
* \| \|	ice40: Fix LUT input indices in opt_lut -dlogic (again).	Marcelina Kościelnicka	2021-07-10	1	-1/+1
* \| \|	Update to latest Verific with extensions for initial assertions	Miodrag Milanovic	2021-07-09	2	-15/+10
* \| \|	sv: fix a few struct and enum memory leaks	Zachary Snow	2021-07-06	2	-2/+11
* \| \|	ecp5: Add DCSC blackbox	gatecat	2021-07-06	1	-0/+10
* \| \|	Merge pull request #2835 from YosysHQ/verific_command	Claire Xen	2021-07-05	1	-0/+61
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\| * \| \|	Add additional help	Miodrag Milanovic	2021-07-05	1	-0/+22
\| * \| \|	Support command files in Verific	Miodrag Milanovic	2021-06-16	1	-0/+39
* \| \| \|	Makefile: allow running multiple sanitizers at once	Xiretza	2021-07-05	1	-3/+3
* \| \| \|	Makefile: use git/make -C instead of cd	Xiretza	2021-07-05	1	-3/+3
* \| \| \|	Makefile: pass PRETTY=0 to ABC	Xiretza	2021-07-05	1	-1/+1
* \| \| \|	Makefile: don't bake DESTDIR into libyosys DT_SONAME	Xiretza	2021-07-05	1	-2/+2
* \| \| \|	Makefile: clean up PYOSYS configuration	Xiretza	2021-07-05	1	-34/+10
* \| \| \|	Merge pull request #2842 from whitequark/fix-wasi-build	whitequark	2021-06-19	1	-1/+1
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\| * \| \| \|	Fix WASI build after commit 1d88bea1.	whitequark	2021-06-19	1	-1/+1
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* \| \| \|	Merge pull request #2836 from YosysHQ/gatecat/pyosys-sigint	Miodrag Milanović	2021-06-18	1	-0/+2
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\| * \| \| \|	pyosys: Clear SIGINT handler after Python loads	gatecat	2021-06-16	1	-0/+2
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* \| \| \|	Move interface expansion in hierarchy.cc into a helper class	Rupert Swarbrick	2021-06-16	1	-100/+189
* \| \| \|	sv: fix up end label checking	Zachary Snow	2021-06-16	7	-7/+98
* \| \| \|	Include blif reader header in public facing extension header files.	Ashton Snelgrove	2021-06-16	1	-0/+1
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* \| \|	verilog: fix leaking of type names in parser	Xiretza	2021-06-14	1	-0/+2
* \| \|	verilog: fix wildcard port connections leaking memory	Xiretza	2021-06-14	1	-0/+1
* \| \|	ast: delete wires and localparams after finishing const evaluation	Xiretza	2021-06-14	1	-0/+8
* \| \|	verilog: fix leaking ASTNodes	Xiretza	2021-06-14	2	-7/+15
* \| \|	ast: fix error condition causing assert to fail	Xiretza	2021-06-14	1	-2/+1
* \| \|	macos: fix leak in proc_self_dirname()	Zachary Snow	2021-06-14	1	-1/+3
* \| \|	Simplify some RTLIL destructors	Rupert Swarbrick	2021-06-14	1	-10/+10
* \| \|	verilog: Squash a memory leak.	Marcelina Kościelnicka	2021-06-14	4	-19/+14
* \| \|	Add regression test for #2824.	Marcelina Kościelnicka	2021-06-11	1	-0/+7
* \| \|	opt_muxtree: Update port_off and port_idx even for constant bits	gatecat	2021-06-11	1	-17/+16