aboutsummaryrefslogtreecommitdiffstats
Commit message (Collapse)AuthorAgeFilesLines
...
| * | | | | | | | | | | | | | ast: Add support for $sformatf system functionDavid Shah2020-01-193-93/+122
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | | | | | | | | | | | | | Merge pull request #1657 from YosysHQ/dave/xilinx-dsp-multonlyDavid Shah2020-02-021-0/+7
|\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | synth_xilinx: add -dsp-multonly
| * | | | | | | | | | | | | | | xilinx_dsp: Add multonly scratchpad var to bypassDavid Shah2020-02-011-0/+7
| |/ / / / / / / / / / / / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | | | | | | | | | | | | | xilinx: use RAM32M/RAM64M for memories with two read portsMarcin Kościelnicki2020-02-021-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This fixes inefficient LUT RAM usage for memories with one write and two read ports (commonly used as register files).
* | | | | | | | | | | | | | | json: remove the 32-bit parameter special caseMarcin Kościelnicki2020-02-011-10/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before, the rules for encoding parameters in JSON were as follows: - if the parameter is not a string: - if it is exactly 32 bits long and there are no z or x bits, emit it as an int - otherwise, emit it as a string made of 0/1/x/z characters - if the parameter is a string: - if it contains only 0/1/x/z characters, append a space at the end to distinguish it from a non-string - otherwise, emit it directly However, this caused a problem in the json11 parser used in nextpnr: yosys emits unsigned ints, and nextpnr parses them as signed, using the value of INT_MIN for values that overflow the signed int range. This caused destruction of LUT5 initialization values. Since both nextpnr and yosys parser can also accept 32-bit parameters in the same encoding as other widths, let's just remove that special case. The old behavior is still left behind a `-compat-int` flag, in case someone relies on it.
* | | | | | | | | | | | | | | Merge pull request #1668 from gsomlo/gls-abc9-externalEddie Hung2020-01-311-0/+1
|\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | abc9: Fix regression breaking support for use of ABCEXTERNAL
| * | | | | | | | | | | | | | | abc9: restore ability to use ABCEXTERNALGabriel Somlo2020-01-301-0/+1
|/ / / / / / / / / / / / / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
* | | | | | | | | | | | | | | Merge pull request #1667 from YosysHQ/clifford/verificnandClaire Wolf2020-01-301-0/+8
|\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add Verific support for OPER_REDUCE_NAND
| * | | | | | | | | | | | | | | Add Verific support for OPER_REDUCE_NANDClaire Wolf2020-01-301-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Claire Wolf <clifford@clifford.at>
* | | | | | | | | | | | | | | | Merge pull request #1503 from YosysHQ/eddie/verific_helpClaire Wolf2020-01-301-8/+8
|\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | `verific` pass to print help message when command syntax error
| * \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ Merge remote-tracking branch 'origin/master' into eddie/verific_helpEddie Hung2020-01-27208-4938/+10113
| |\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \
| * | | | | | | | | | | | | | | | | verific: no help() when no YOSYS_ENABLE_VERIFICEddie Hung2020-01-271-4/+1
| | | | | | | | | | | | | | | | | |
| * | | | | | | | | | | | | | | | | OopsEddie Hung2019-11-191-1/+1
| | | | | | | | | | | | | | | | | |
| * | | | | | | | | | | | | | | | | Print help message for verific passEddie Hung2019-11-191-9/+12
| | | | | | | | | | | | | | | | | |
* | | | | | | | | | | | | | | | | | Merge pull request #1654 from YosysHQ/eddie/sby_fix69Claire Wolf2020-01-301-0/+6
|\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | |_|_|/ / / / / / / / / / / / / / / |/| | | | | | | | | | | | | | | | | verific: unflatten struct ports
| * | | | | | | | | | | | | | | | | verific: also unflatten for 'hierarchy' flow as per @cliffordwolfEddie Hung2020-01-271-0/+3
| | | | | | | | | | | | | | | | | |
| * | | | | | | | | | | | | | | | | verific: unflatten struct portsEddie Hung2020-01-241-0/+3
| | |/ / / / / / / / / / / / / / / | |/| | | | | | | | | | | | | | |
* | | | | | | | | | | | | | | | | Merge branch 'vector_fix' of https://github.com/Kmanfi/yosysClaire Wolf2020-01-291-1/+3
|\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Also some minor fixes to the original PR.
| * | | | | | | | | | | | | | | | | Fix input vector for reduce cells. Infinite loop fixed.Kaj Tuomi2017-10-171-0/+2
| | | | | | | | | | | | | | | | | |
| * | | | | | | | | | | | | | | | | Merge branch 'master' of https://github.com/cliffordwolf/yosys into vector_fixKaj Tuomi2017-10-173-1/+54
| |\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \
| * | | | | | | | | | | | | | | | | | Add Verific fairness/liveness supportClifford Wolf2017-10-121-11/+32
| | | | | | | | | | | | | | | | | | |
* | | | | | | | | | | | | | | | | | | Merge pull request #1662 from YosysHQ/dave/opt-reduce-move-checkClaire Wolf2020-01-291-1/+2
|\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | opt_reduce: Call check() per run rather than per optimised cell
| * | | | | | | | | | | | | | | | | | | opt_reduce: Call check() per run rather than per optimised cellDavid Shah2020-01-281-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | | | | | | | | | | | | | | | | | | Merge pull request #1665 from YosysHQ/clifford/edifkeepClaire Wolf2020-01-291-9/+34
|\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Preserve wires with keep attribute in EDIF back-end
| * | | | | | | | | | | | | | | | | | | | Preserve wires with keep attribute in EDIF back-endClaire Wolf2020-01-291-9/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Claire Wolf <clifford@clifford.at>
* | | | | | | | | | | | | | | | | | | | | Merge pull request #1659 from YosysHQ/clifford/experimentalClaire Wolf2020-01-296-4/+56
|\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add log_experimental() and experimental() API and "yosys -x"
| * | | | | | | | | | | | | | | | | | | | | Improve logging use of experimental featuresClaire Wolf2020-01-283-4/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Claire Wolf <clifford@clifford.at>
| * | | | | | | | | | | | | | | | | | | | | Add log_experimental() and experimental() API and "yosys -x"Claire Wolf2020-01-276-4/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Claire Wolf <clifford@clifford.at>
* | | | | | | | | | | | | | | | | | | | | | Merge pull request #1510 from pumbor/masterN. Engelhardt2020-01-291-0/+13
|\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | handle anonymous unions to fix #1080
| * | | | | | | | | | | | | | | | | | | | | | handle anonymous unions to fix #1080Patrick Eibl2019-11-211-0/+13
| | | | | | | | | | | | | | | | | | | | | | |
* | | | | | | | | | | | | | | | | | | | | | | Merge pull request #1559 from YosysHQ/efinix_test_fixMiodrag Milanović2020-01-291-1/+1
|\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix for non-deterministic test
| * | | | | | | | | | | | | | | | | | | | | | | Updated test to use assert-maxMiodrag Milanovic2020-01-281-1/+1
| | | | | | | | | | | | | | | | | | | | | | | |
| * | | | | | | | | | | | | | | | | | | | | | | Fix for non-deterministic testMiodrag Milanovic2019-12-071-1/+1
| | | | | | | | | | | | | | | | | | | | | | | |
* | | | | | | | | | | | | | | | | | | | | | | | Add "help -all" and "help -celltypes" sanity testEddie Hung2020-01-281-0/+2
| | | | | | | | | | | | | | | | | | | | | | | |
* | | | | | | | | | | | | | | | | | | | | | | | synth_xilinx: cleanup helpEddie Hung2020-01-281-6/+4
| | | | | | | | | | | | | | | | | | | | | | | |
* | | | | | | | | | | | | | | | | | | | | | | | synth_xilinx: fix help when no active_design; fixes #1664Eddie Hung2020-01-281-2/+3
| | | | | | | | | | | | | | | | | | | | | | | |
* | | | | | | | | | | | | | | | | | | | | | | | xilinx: Add simulation model for DSP48 (Virtex 4).Marcin Kościelnicki2020-01-296-45/+534
| | | | | | | | | | | | | | | | | | | | | | | |
* | | | | | | | | | | | | | | | | | | | | | | | Merge pull request #1660 from YosysHQ/eddie/abc9_unpermute_lutsEddie Hung2020-01-289-149/+207
|\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Unpermute LUT ordering for ice40/ecp5/xilinx
| * | | | | | | | | | | | | | | | | | | | | | | | Add and use SigSpec::reverse()Eddie Hung2020-01-282-3/+5
| | | | | | | | | | | | | | | | | | | | | | | | |
| * | | | | | | | | | | | | | | | | | | | | | | | Fix $lut input ordering -- SigSpec(std::initializer_list<>) is backwardsEddie Hung2020-01-272-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Just like Verilog...
| * | | | | | | | | | | | | | | | | | | | | | | | Import tests from #1628Eddie Hung2020-01-273-2/+104
| | | | | | | | | | | | | | | | | | | | | | | | |
| * | | | | | | | | | | | | | | | | | | | | | | | xilinx/ice40/ecp5: undo permuting LUT masks in lut_mapEddie Hung2020-01-274-148/+102
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now done in read_aiger
* | | | | | | | | | | | | | | | | | | | | | | | | Fix unresolved conflict from #1573Eddie Hung2020-01-281-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | |
* | | | | | | | | | | | | | | | | | | | | | | | | Merge pull request #1567 from YosysHQ/eddie/sat_init_warningClaire Wolf2020-01-282-1/+13
|\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | |_|_|_|_|/ / / / / / / / / / / / / / / / / / / / |/| | | | | | | | | | | | | | | | | | | | | | | | sat: suppress 'Warning: ignoring initial value on non-register: ...' when init[i] = 1'bx
| * | | | | | | | | | | | | | | | | | | | | | | | Even more obvious testcaseEddie Hung2019-12-111-6/+5
| | | | | | | | | | | | | | | | | | | | | | | | |
| * | | | | | | | | | | | | | | | | | | | | | | | Make testcase clearer with \o having its own initEddie Hung2019-12-111-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | |
| * | | | | | | | | | | | | | | | | | | | | | | | Suppress warning message for init[i] = 1'bxEddie Hung2019-12-111-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | |
| * | | | | | | | | | | | | | | | | | | | | | | | Add test: 'Warning: ignoring initial value on non-register: \o'Eddie Hung2019-12-111-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | |
* | | | | | | | | | | | | | | | | | | | | | | | | Merge pull request #1573 from YosysHQ/eddie/xilinx_tristateN. Engelhardt2020-01-283-1/+13
|\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | |_|_|_|_|_|/ / / / / / / / / / / / / / / / / / / |/| | | | | | | | | | | | | | | | | | | | | | | | synth_xilinx: error out if tristate without '-iopad'
| * | | | | | | | | | | | | | | | | | | | | | | | Duplicate tribuf call, credit to @mwkmwkmwkEddie Hung2019-12-131-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | |
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-09 00:46:51 +0000