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* Merge branch 'master' into eddie/muxpackEddie Hung2019-06-0739-364/+573
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| * Fix spacing from spaces to tabsEddie Hung2019-06-071-362/+362
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| * Merge pull request #1079 from YosysHQ/eddie/fix_read_aigerClifford Wolf2019-06-0727-45/+128
| |\ | | | | | | Fix read_aiger to really get tested, and fix some uncovered read_aiger issues
| | * Add read_aiger to CHANGELOGEddie Hung2019-06-071-0/+1
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| | * Fix spacing (entire file is wrong anyway, will fix later)Eddie Hung2019-06-071-3/+3
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| | * Remove unnecessary std::getline() for ASCIIEddie Hung2019-06-071-3/+0
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| | * Test *.aag too, by using *.aig as referenceEddie Hung2019-06-071-0/+19
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| | * Fix read_aiger -- create zero driver, fix init width, parse 'b'Eddie Hung2019-06-072-13/+52
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| | * Use ABC to convert from AIGER to VerilogEddie Hung2019-06-071-2/+3
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| | * Use ABC to convert AIGER to Verilog, then sat against YosysEddie Hung2019-06-071-21/+15
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| | * Add symbols to AIGER test inputs for ABCEddie Hung2019-06-0722-8/+40
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| * Merge pull request #1077 from YosysHQ/clifford/pr983Clifford Wolf2019-06-079-3/+93
| |\ | | | | | | elaboration system tasks
| | * Fixes and cleanups in AST_TECALL handlingClifford Wolf2019-06-074-50/+38
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * Merge branch 'pr_elab_sys_tasks' of https://github.com/udif/yosys into ↵Clifford Wolf2019-06-0710-5/+107
| | |\ | | | | | | | | | | | | clifford/pr983
| | | * Initial implementation of elaboration system tasksUdi Finkelstein2019-05-0310-5/+107
| | | | | | | | | | | | | | | | | | | | | | | | | | | | (IEEE1800-2017 section 20.11) This PR allows us to use $info/$warning/$error/$fatal **at elaboration time** within a generate block. This is very useful to stop a synthesis of a parametrized block when an illegal combination of parameters is chosen.
| * | | Rename implicit_ports.sv test to implicit_ports.vClifford Wolf2019-06-071-0/+0
| |/ / | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Merge branch 'tux3-implicit_named_connection'Clifford Wolf2019-06-074-3/+40
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| | * | Cleanup tux3-implicit_named_connectionClifford Wolf2019-06-073-13/+2
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * | Merge branch 'implicit_named_connection' of https://github.com/tux3/yosys ↵Clifford Wolf2019-06-075-4/+52
| | |\ \ | | | | | | | | | | | | | | | into tux3-implicit_named_connection
| | | * | SystemVerilog support for implicit named port connectionstux32019-06-065-12/+59
| | | | | | | | | | | | | | | | | | | | | | | | | This is the `foo foo(.port1, .port2);` SystemVerilog syntax introduced in IEEE1800-2005.
| * | | | Merge pull request #1076 from thasti/centos7-build-fixClifford Wolf2019-06-071-1/+0
| |\ \ \ \ | | |/ / / | |/| | | Fix pyosys-build on CentOS7
| | * | | remove boost/log/exceptions.hpp from wrapper generatorStefan Biereigel2019-06-071-1/+0
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* | | | Comment O(N) -> O(N^2)Eddie Hung2019-06-071-1/+1
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* | | | Add nonexcl case test, comment out two othersEddie Hung2019-06-072-22/+57
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* | | | Extend ExclusiveDatabase to query SigSpec-s (for $pmux)Eddie Hung2019-06-071-19/+27
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* | | | Add ExclusiveDatabase to check exclusive $eq/$logic_not cell resultsEddie Hung2019-06-071-1/+64
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* | | | Add @cliffordwolf freduce testcaseEddie Hung2019-06-072-0/+30
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* | | | Add nonexclusive test from @cliffordwolfEddie Hung2019-06-072-0/+28
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* | | | Resolve @cliffordwolf comment on redundant checkEddie Hung2019-06-071-10/+2
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* | | | Resolve @cliffordwolf comment on sigmapEddie Hung2019-06-071-2/+2
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* | | | Another muxpack testEddie Hung2019-06-072-0/+32
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* | | | Fix and test for balanced caseEddie Hung2019-06-063-10/+55
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* | | | Fix warningsEddie Hung2019-06-062-3/+3
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* | | | Support cascading $pmux.A with $mux.A and $mux.BEddie Hung2019-06-063-17/+65
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* | | | More cleanupEddie Hung2019-06-061-15/+20
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* | | | Fix spacingEddie Hung2019-06-061-6/+5
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* | | | Non chain user check using next_sigEddie Hung2019-06-061-7/+5
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* | | | Add non exclusive testEddie Hung2019-06-062-0/+56
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* | | | Move muxpack from passes/techmap to passes/optEddie Hung2019-06-063-1/+1
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* | | | Update docEddie Hung2019-06-061-4/+5
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* | | | Add to CHANGELOGEddie Hung2019-06-061-0/+1
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* | | | One more and tidy upEddie Hung2019-06-062-6/+28
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* | | | Add a few more special case testsEddie Hung2019-06-062-0/+51
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* | | | Add tests, fix for !=Eddie Hung2019-06-063-9/+110
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* | | | Missing fileEddie Hung2019-06-061-0/+232
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* | | | Initial adaptation of muxpack from shregmapEddie Hung2019-06-061-0/+1
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* | | Merge pull request #1060 from antmicro/parsing_attr_on_port_connClifford Wolf2019-06-0614-10/+279
|\ \ \ | | | | | | | | Added support for parsing attributes on port connections.
| * | | Fixed memory leak.Maciej Kurc2019-06-051-0/+4
| | | | | | | | | | | | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
| * | | Moved tests that fail with Icarus Verilog to /tests/various. Those tests are ↵Maciej Kurc2019-06-044-0/+46
| | | | | | | | | | | | | | | | | | | | | | | | just for parsing Verilog. Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
| * | | Added tests for attributesMaciej Kurc2019-06-039-0/+219
| | | | | | | | | | | | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
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