| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| * | | | | | Merge branch 'whitequark-write_verilog_keyword' | Clifford Wolf | 2019-01-27 | 5 | -69/+27 | |
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| | * | | | | Remove asicworld tests for (unsupported) switch-level modelling | Clifford Wolf | 2019-01-27 | 4 | -69/+0 | |
| | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | | | | write_verilog: escape names that match SystemVerilog keywords. | whitequark | 2019-01-27 | 1 | -0/+27 | |
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| * | | | | Merge pull request #796 from whitequark/proc_clean_typo | David Shah | 2019-01-25 | 1 | -1/+1 | |
| |\ \ \ \ | |/ / / |/| | | | proc_clean: fix critical typo | |||||
| | * | | | proc_clean: fix critical typo. | whitequark | 2019-01-23 | 1 | -1/+1 | |
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| * | | | Merge pull request #793 from whitequark/proc_clean_fix_fully_def | Clifford Wolf | 2019-01-19 | 1 | -1/+7 | |
| |\ \ \ | | | | | | | | | proc_clean: fix fully def check to consider compare/signal length | |||||
| | * | | | proc_clean: fix fully def check to consider compare/signal length. | whitequark | 2019-01-18 | 1 | -1/+7 | |
| |/ / / | | | | | | | | | | Fixes #790. | |||||
| * | | | Cleanups in igloo2 example design | Clifford Wolf | 2019-01-17 | 6 | -7/+4 | |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | | Add SF2 IO buffer insertion | Clifford Wolf | 2019-01-17 | 6 | -3/+171 | |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | | Improve Igloo2 example | Clifford Wolf | 2019-01-17 | 8 | -22/+41 | |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | | Add "synth_sf2 -vlog", fix "synth_sf2 -edif" | Clifford Wolf | 2019-01-17 | 1 | -2/+17 | |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | | Add "write_edif -gndvccy" | Clifford Wolf | 2019-01-17 | 1 | -5/+13 | |
| |/ / | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | Add optional nullstr argument to log_id() | Clifford Wolf | 2019-01-15 | 1 | -1/+3 | |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | Fix handling of $shiftx in Verilog back-end | Clifford Wolf | 2019-01-15 | 1 | -3/+6 | |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | Merge pull request #788 from whitequark/master | Clifford Wolf | 2019-01-15 | 1 | -5/+17 | |
| |\ \ | | | | | | | Document $tribuf and some gates | |||||
| | * | | manual: document some gates. | whitequark | 2019-01-14 | 1 | -9/+11 | |
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| | * | | manual: explain $tribuf cell. | whitequark | 2019-01-14 | 1 | -0/+10 | |
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| * | | | Merge pull request #787 from whitequark/flowmap_relax | Clifford Wolf | 2019-01-15 | 7 | -35/+776 | |
| |\ \ \ | |/ / |/| | | flowmap: implement depth relaxation | |||||
| | * | | flowmap: clean up terminology. | whitequark | 2019-01-08 | 1 | -17/+18 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * "map": group gates into LUTs; * "pack": replace gates with LUTs. This is important because we have FlowMap and DF-Map, and currently our messages are ambiguous. Also clean up some other log messages while we're at it. | |||||
| | * | | flowmap: implement depth relaxation. | whitequark | 2019-01-08 | 7 | -22/+762 | |
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| * | | | Improve igloo2 example | Clifford Wolf | 2019-01-08 | 4 | -5/+29 | |
| |/ / | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | Fix typo in manual | Clifford Wolf | 2019-01-07 | 1 | -1/+1 | |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | Bugfix in $memrd sharing | Clifford Wolf | 2019-01-07 | 1 | -2/+6 | |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | Merge pull request #782 from whitequark/flowmap_dfs | Clifford Wolf | 2019-01-07 | 3 | -124/+243 | |
| |\ \ | | | | | | | flowmap: construct a max-volume max-flow min-cut, not just any one | |||||
| | * | | flowmap: construct a max-volume max-flow min-cut, not just any one. | whitequark | 2019-01-06 | 1 | -7/+10 | |
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| | * | | flowmap: add -minlut option, to allow postprocessing with opt_lut. | whitequark | 2019-01-04 | 1 | -7/+21 | |
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| | * | | flowmap: cleanup for clarity. NFCI. | whitequark | 2019-01-04 | 3 | -107/+179 | |
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| | * | | flowmap: improve debug graph output. NFC. | whitequark | 2019-01-04 | 1 | -47/+76 | |
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| | * | | flowmap: add link to longer version of paper. NFC. | whitequark | 2019-01-04 | 1 | -2/+3 | |
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| * | | | Switch "bugpoint" from system() to run_command() | Clifford Wolf | 2019-01-07 | 1 | -1/+1 | |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | | Merge pull request #783 from whitequark/bugpoint | Clifford Wolf | 2019-01-07 | 2 | -1/+370 | |
| |\ \ \ | | | | | | | | | bugpoint: new pass | |||||
| | * | | | bugpoint: new pass. | whitequark | 2019-01-07 | 2 | -1/+370 | |
| |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A typical use of `bugpoint` would involve a script with a pass under test, e.g.: flowmap -relax -optarea 100 and would be invoked as: bugpoint -yosys ./yosys -script flowmap.ys -clean -cells This replaces the current design with the minimal design that still crashes the `flowmap.ys` script. `bugpoint` can also be used to perform generic design minimization using `select`, e.g. the following script: select i:* %x t:$_MUX_ %i -assert-max 0 would remove all parts of the design except for an unbroken path from an input to an output port that goes through exactly one $_MUX_ cell. (The condition is inverted.) | |||||
| * | | | Merge pull request #780 from phire/rename_from_wire | Clifford Wolf | 2019-01-06 | 1 | -0/+66 | |
| |\ \ \ | | | | | | | | | Rename cells based on the wires they drive. | |||||
| | * | | | Rename cells based on the wires they drive. | Scott Mansell | 2019-01-06 | 1 | -0/+66 | |
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| * | | | | Add skeleton Yosys-Libero igloo2 example project | Clifford Wolf | 2019-01-05 | 5 | -0/+44 | |
| | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | | | Bugfix in Verilog string handling | Clifford Wolf | 2019-01-05 | 1 | -1/+1 | |
| |/ / / | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | | Merge pull request #777 from mmicko/achronix_cell_sim_fix | Clifford Wolf | 2019-01-04 | 1 | -1/+1 | |
| |\ \ \ | | | | | | | | | Fix cells_sim.v for Achronix FPGA | |||||
| | * | | | Fix cells_sim.v for Achronix FPGA | Miodrag Milanovic | 2019-01-04 | 1 | -1/+1 | |
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| * | | | Remove -m32 Verific eval lib build instructions | Clifford Wolf | 2019-01-04 | 1 | -29/+0 | |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | | Merge pull request #776 from mmicko/unify_noflatten | Clifford Wolf | 2019-01-04 | 4 | -8/+16 | |
| |\ \ \ | | | | | | | | | Unify usage of noflatten among architectures | |||||
| | * | | | Unify usage of noflatten among architectures | Miodrag Milanovic | 2019-01-04 | 4 | -8/+16 | |
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| * / / | Update Verific default path | Clifford Wolf | 2019-01-04 | 1 | -1/+1 | |
| |/ / | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | Merge pull request #775 from whitequark/opt_flowmap | Clifford Wolf | 2019-01-03 | 3 | -1/+875 | |
| |\ \ | | | | | | | flowmap: new techmap pass | |||||
| | * | | flowmap: new techmap pass. | whitequark | 2019-01-03 | 3 | -1/+875 | |
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| * | | | Merge pull request #770 from whitequark/opt_expr_cmp | Clifford Wolf | 2019-01-02 | 3 | -97/+178 | |
| |\ \ \ | |/ / |/| | | opt_expr: refactor and improve simplification of comparisons | |||||
| | * | | opt_expr: improve simplification of comparisons with large constants. | whitequark | 2019-01-02 | 2 | -70/+65 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The idea behind this simplification is that a N-bit signal X being compared with an M-bit constant where M>N and the constant has Nth or higher bit set, it either always succeeds or always fails. However, the existing implementation only worked with one-hot signals for some reason. It also printed incorrect messages. This commit adjusts the simplification to have as much power as possible, and fixes other bugs. | |||||
| | * | | opt_expr: refactor simplification of unsigned X<onehot and X>=onehot. NFCI. | whitequark | 2019-01-02 | 2 | -31/+42 | |
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| | * | | opt_expr: refactor simplification of signed X>=0 and X<0. NFCI. | whitequark | 2019-01-02 | 2 | -32/+40 | |
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| | * | | opt_expr: simplify any unsigned comparisons with all-0 and all-1. | whitequark | 2019-01-02 | 3 | -17/+84 | |
| | | | | | | | | | | | | | | | | | | | Before this commit, only unsigned comparisons with all-0 would be simplified. This commit also makes the code handling such comparisons to be more rigorous and not abort on unexpected input. | |||||
| * | | | Merge pull request #755 from Icenowy/anlogic-dram-init | Clifford Wolf | 2019-01-02 | 6 | -2/+96 | |
| |\ \ \ | | | | | | | | | anlogic: implement DRAM initialization | |||||
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index : iCE40/yosys | |
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