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Bump version
github-actions[bot]
2022-10-21
1
-1
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+1
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Add missing log_dump handler for std::vector<>
Claire Xenia Wolf
2022-10-20
1
-0
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+12
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Bump version
github-actions[bot]
2022-10-20
1
-1
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+1
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Temporal induction counterexample loop detection (#3504)
Emil J
2022-10-19
1
-1
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+36
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Merge pull request #3514 from jix/smtbmc-kind-witness-fix
Jannis Harder
2022-10-19
1
-1
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+1
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smtbmc: Fix witness handling for k-induction failures
Jannis Harder
2022-10-18
1
-1
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+1
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Bump version
github-actions[bot]
2022-10-15
1
-1
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+1
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Merge pull request #3511 from YosysHQ/improve_edif
Miodrag Milanović
2022-10-14
1
-1
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+31
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Skip verific primitives and operators import by default
Miodrag Milanovic
2022-10-14
1
-0
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+1
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Add option to import all cells from all libraries
Miodrag Milanovic
2022-10-14
1
-1
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+30
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Bump version
github-actions[bot]
2022-10-13
1
-1
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+1
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Merge pull request #3510 from jix/ff_witness_fixes
Jannis Harder
2022-10-12
4
-12
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+29
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smt2/smtbmc: Fix FF witness data for fine grained or multi chunk FFs
Jannis Harder
2022-10-12
4
-12
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+29
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github: issues: added an OS dropdown to the issue template
Aki Van Ness
2022-10-12
1
-1
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+13
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Merge pull request #3502 from jix/equiv_opt_fixes
Jannis Harder
2022-10-11
28
-267
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+207
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Reenable existing equiv_opt tests
Jannis Harder
2022-10-07
13
-54
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+52
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Fix tests for check in equiv_opt
Jannis Harder
2022-10-07
13
-15
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+31
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Add "check -assert" to equiv_opt
Claire Xenia Wolf
2022-10-07
1
-1
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+13
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Re-enable opt_dff_sr equiv_opt checks
Claire Xenia Wolf
2022-10-07
1
-13
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+12
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Exclude primary inputs from quiv_make rewiring
Claire Xenia Wolf
2022-10-07
1
-0
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+7
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Revert "Merge pull request #641 from tklam/master"
Claire Xenia Wolf
2022-10-07
1
-81
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+5
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clk2fflogic: Always correctly handle simultaneously changing signals
Jannis Harder
2022-10-07
1
-103
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+87
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Bump version
github-actions[bot]
2022-10-11
1
-1
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+1
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Merge pull request #3508 from YosysHQ/aki/rm_protobuf
Miodrag Milanović
2022-10-10
5
-562
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+0
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backends: protobuf: removed protobuf backend
Aki Van Ness
2022-10-10
5
-562
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+0
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fix whitespace
Miodrag Milanovic
2022-10-10
1
-1
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+1
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Merge pull request #3452 from ALGCDG/master
Miodrag Milanović
2022-10-10
2
-1
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+17
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Changing error reason string to be based on lut input plane limit constant.
Archie
2022-10-02
1
-1
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+1
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Adding check for BLIF names command input plane size.
Archie
2022-08-21
2
-1
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+17
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Merge branch 'master' of https://github.com/ALGCDG/yosys
Archie
2022-08-21
81
-737
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+4859
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Adding expected error message.
Archie
2022-06-20
1
-0
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+1
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Adding testcase for issue 3374
Archie
2022-06-17
1
-0
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+3
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Add check for BLIF with no model name
Archie
2022-06-14
1
-1
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+4
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Merge pull request #3507 from YosysHQ/claire/verificlibopt
Miodrag Milanović
2022-10-10
1
-0
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+14
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Fix handling of verific -L options, add implicit "-L work"
Claire Xenia Wolf
2022-10-10
1
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+14
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Bump version
github-actions[bot]
2022-10-08
1
-1
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+1
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Merge pull request #3503 from jix/abort_on_log_error
Jannis Harder
2022-10-07
2
-0
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+7
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Add YOSYS_ABORT_ON_LOG_ERROR environment variable for debugging.
Jannis Harder
2022-10-07
2
-0
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+7
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Bump version
github-actions[bot]
2022-10-06
1
-1
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+1
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Next dev cycle
Miodrag Milanovic
2022-10-05
2
-2
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+5
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Release version 0.22
Miodrag Milanovic
2022-10-05
2
-3
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+3
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Update CHANGELOG
Miodrag Milanovic
2022-10-05
1
-0
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+8
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Merge pull request #3500 from nakengelhardt/mutate_warn_not_enough
Miodrag Milanović
2022-10-05
1
-0
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+2
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mutate: warn if less mutations possible than number requested
N. Engelhardt
2022-10-05
1
-0
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+2
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Merge pull request #3499 from YosysHQ/micko/verific_edif
Miodrag Milanović
2022-10-05
2
-1
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+52
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Add support for EDIF file reading using Verific
Miodrag Milanovic
2022-10-04
2
-1
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+52
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Bump version
github-actions[bot]
2022-10-05
1
-1
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+1
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Merge pull request #3494 from YosysHQ/micko/verific_attributes
Miodrag Milanović
2022-10-04
1
-19
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+91
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support file content redirection for verific frontened
Miodrag Milanovic
2022-09-28
1
-14
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+60
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Add comment for future self
Miodrag Milanovic
2022-09-28
1
-0
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+7
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