iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
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\| * \| \| \| \| \| \| \| \|	Merge pull request #1322 from mmicko/pyosys_osx	Eddie Hung	2019-08-22	1	-0/+2
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\| \| * \| \| \| \| \| \| \| \|	do not require boost if pyosys is not used	Miodrag Milanovic	2019-08-22	1	-0/+2
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\| * \| \| \| \| \| \| \| \|	Merge pull request #1319 from TeaEngineering/shuckc/brew-tcl-tk	Eddie Hung	2019-08-22	1	-0/+1
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\| \| * \| \| \| \| \| \| \|	require tcl-tk in Brewfile	Chris Shucksmith	2019-08-22	1	-0/+1
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\| * \| \| \| \| \| \| \|	Merge pull request #1317 from YosysHQ/eddie/opt_expr_shiftx	Eddie Hung	2019-08-22	2	-4/+96
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\| \| * \| \| \| \| \| \| \|	Copy-paste typo	Eddie Hung	2019-08-22	1	-1/+1
\| \| * \| \| \| \| \| \| \|	Respect opt_expr -keepdc as per @cliffordwolf	Eddie Hung	2019-08-22	2	-1/+15
\| \| * \| \| \| \| \| \| \|	Handle $shift and Y_WIDTH > 1 as per @cliffordwolf	Eddie Hung	2019-08-22	2	-5/+51
\| \| * \| \| \| \| \| \| \|	Add cover()	Eddie Hung	2019-08-22	1	-0/+1
\| \| * \| \| \| \| \| \| \|	Canonical form	Eddie Hung	2019-08-22	1	-5/+5
\| \| * \| \| \| \| \| \| \|	Add test	Eddie Hung	2019-08-21	1	-0/+14
\| \| * \| \| \| \| \| \| \|	opt_expr to trim A port of $shiftx if Y_WIDTH == 1	Eddie Hung	2019-08-21	1	-0/+17
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\| * \| \| \| \| \| \| \|	Bump year in copyright notice	Clifford Wolf	2019-08-22	3	-3/+3
\| * \| \| \| \| \| \| \|	Fix missing newline at end of file	Clifford Wolf	2019-08-22	1	-1/+1
\| * \| \| \| \| \| \| \|	Merge pull request #1289 from mmicko/anlogic_fixes	Clifford Wolf	2019-08-22	5	-91/+162
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\| \| * \ \ \ \ \ \ \	Merge remote-tracking branch 'upstream/master' into anlogic_fixes	Miodrag Milanovic	2019-08-18	109	-3621/+4745
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\| \| * \| \| \| \| \| \| \| \|	Proper arith for Anlogic and use standard pass	Miodrag Milanovic	2019-08-12	5	-91/+162
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\| * \| \| \| \| \| \| \| \|	Fix missing newline at end of file	Clifford Wolf	2019-08-22	1	-1/+1
\| * \| \| \| \| \| \| \| \|	Merge pull request #1281 from mmicko/efinix	Clifford Wolf	2019-08-22	9	-0/+798
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\| \| * \| \| \| \| \| \| \|	Fix formating	Miodrag Milanovic	2019-08-11	1	-2/+2
\| \| * \| \| \| \| \| \| \|	one bit enable signal	Miodrag Milanovic	2019-08-11	1	-1/+1
\| \| * \| \| \| \| \| \| \|	fix mixing signals on FF mapping	Miodrag Milanovic	2019-08-11	1	-4/+4
\| \| * \| \| \| \| \| \| \|	Replaced custom step with setundef	Miodrag Milanovic	2019-08-11	3	-91/+1
\| \| * \| \| \| \| \| \| \|	Fixed data width	Miodrag Milanovic	2019-08-11	1	-2/+2
\| \| * \| \| \| \| \| \| \|	Adding new pass to fix carry chain	Miodrag Milanovic	2019-08-11	3	-0/+124
\| \| * \| \| \| \| \| \| \|	cleanup	Miodrag Milanovic	2019-08-11	1	-4/+7
\| \| * \| \| \| \| \| \| \|	Fix CO	Miodrag Milanovic	2019-08-09	1	-26/+24
\| \| * \| \| \| \| \| \| \|	Merge remote-tracking branch 'upstream/master' into efinix	Miodrag Milanovic	2019-08-09	58	-598/+1321
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\| \| * \| \| \| \| \| \| \| \|	clock for ram trough gbuf	Miodrag Milanovic	2019-08-04	1	-0/+6
\| \| * \| \| \| \| \| \| \| \|	Added bram support	Miodrag Milanovic	2019-08-04	6	-1/+260
\| \| * \| \| \| \| \| \| \| \|	Custom step to add global clock buffers	Miodrag Milanovic	2019-08-03	4	-1/+129
\| \| * \| \| \| \| \| \| \| \|	Initial EFINIX support	Miodrag Milanovic	2019-08-03	5	-0/+370
\| * \| \| \| \| \| \| \| \| \|	Merge pull request #1316 from YosysHQ/eddie/fix_mem2reg	Clifford Wolf	2019-08-22	2	-0/+17
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\| \| * \| \| \| \| \| \| \| \|	mem2reg to preserve user attributes and src	Eddie Hung	2019-08-21	2	-0/+17
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\| * \| \| \| \| \| \| \| \|	Merge pull request #1315 from mmicko/fix_dependencies	whitequark	2019-08-21	1	-1/+1
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\| \| * \| \| \| \| \| \| \|	Fix test_pmgen deps	Miodrag Milanovic	2019-08-21	1	-1/+1
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* \| \| \| \| \| \| \| \|	Use semicolon	Eddie Hung	2019-08-21	1	-1/+1
* \| \| \| \| \| \| \| \|	techmap before read	Eddie Hung	2019-08-21	1	-1/+1
* \| \| \| \| \| \| \| \|	Merge remote-tracking branch 'origin/master' into xaig_arrival	Eddie Hung	2019-08-21	0	-0/+0
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\| * \| \| \| \| \| \| \|	Merge pull request #1314 from YosysHQ/eddie/fix_techmap	Clifford Wolf	2019-08-21	4	-4/+21
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* \| \| \| \| \| \| \| \| \|	Merge remote-tracking branch 'origin/master' into xaig_arrival	Eddie Hung	2019-08-21	2	-2/+2
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\| * \| \| \| \| \| \| \| \|	Missing newline	Eddie Hung	2019-08-20	1	-1/+1
\| * \| \| \| \| \| \| \| \|	Fix copy-paste typo	Eddie Hung	2019-08-20	1	-1/+1
* \| \| \| \| \| \| \| \| \|	Output "h" extension only if boxes	Eddie Hung	2019-08-21	1	-28/+32
* \| \| \| \| \| \| \| \| \|	Revert "Fix omode which inserts an output if none exists (otherwise abc9 brea...	Eddie Hung	2019-08-21	1	-8/+7
* \| \| \| \| \| \| \| \| \|	Add abc_arrival to SRL*	Eddie Hung	2019-08-21	1	-3/+5
* \| \| \| \| \| \| \| \| \|	Fix omode which inserts an output if none exists (otherwise abc9 breaks)	Eddie Hung	2019-08-20	1	-7/+8
* \| \| \| \| \| \| \| \| \|	Revert "Only xaig if GetSize(output_bits) > 0"	Eddie Hung	2019-08-20	1	-149/+147
* \| \| \| \| \| \| \| \| \|	Only xaig if GetSize(output_bits) > 0	Eddie Hung	2019-08-20	1	-147/+149
* \| \| \| \| \| \| \| \| \|	Oops	Eddie Hung	2019-08-20	1	-1/+1