| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | proc_prune: promote assigns to module connections when legal. | whitequark | 2019-07-09 | 3 | -33/+42 |
| | | | | | | | | | | | This can pave the way for further transformations by exposing identities that were previously hidden in a process to any pass that uses SigMap. Indeed, this commit removes some ad-hoc logic from proc_init that appears to have been tailored to the output of genrtlil in favor of using `SigMap.apply()`. (This removal is not optional, as the ad-hoc logic cannot cope with the result of running proc_prune; a similar issue was fixed in proc_arst.) | ||||
| * | proc_prune: new pass. | whitequark | 2019-07-09 | 3 | -1/+138 |
| | | | | | | | | | | | | | | | | | | | The proc_prune pass is similar in nature to proc_rmdead pass: while proc_rmdead removes branches that never become active because another branch preempts it, proc_prune removes assignments that never become active because another assignment preempts them. Genrtlil contains logic similar to the proc_prune pass, but their purpose is different: genrtlil has to prune assignments to adapt the semantics of blocking assignments in HDLs (latest assignment wins) to semantics of assignments in RTLIL processes (assignment in the most specific case wins). On the other hand proc_prune is a general purpose RTLIL simplification that benefits all frontends, even those not using the Yosys AST library. The proc_prune pass is added to the proc script after proc_rmdead, since it gives better results with fewer branches. | ||||
| * | Merge pull request #1159 from btut/fix/1090_segfault_cell_and_wire | Clifford Wolf | 2019-07-05 | 1 | -0/+3 |
| |\ | | | | | Throw runtime exception when trying to convert inexistend C++ object to Python | ||||
| | * | Throw runtime exception when trying to convert a c++-pointer to a | Benedikt Tutzer | 2019-07-04 | 1 | -0/+3 |
| |/ | | | | | | python-object in case the pointer is a nullptr to avoid a segfault. Fixes #1090 | ||||
| * | Merge pull request #1156 from YosysHQ/eddie/fix_abc9_unknown_cell | Eddie Hung | 2019-07-03 | 3 | -6/+28 |
| |\ | | | | | write_xaiger to treat unknown cell connections as keep-s | ||||
| | * | write_xaiger to treat unknown cell connections as keep-s | Eddie Hung | 2019-07-02 | 1 | -6/+14 |
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| | * | Add test | Eddie Hung | 2019-07-02 | 2 | -0/+14 |
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| * | | Merge pull request #1147 from YosysHQ/clifford/fix1144 | Clifford Wolf | 2019-07-03 | 3 | -82/+26 |
| |\ \ | | | | | | | Improve specify dummy parser | ||||
| | * | | Fix tests/various/specify.v | Clifford Wolf | 2019-07-03 | 2 | -8/+3 |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| | * | | Some cleanups in "ignore specify parser" | Clifford Wolf | 2019-07-03 | 2 | -80/+6 |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| | * | | Comment out invalid syntax | Eddie Hung | 2019-06-30 | 1 | -2/+2 |
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| | * | | Add test from #1144, and try reading without '-specify' flag | Eddie Hung | 2019-06-28 | 2 | -0/+16 |
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| | * | | Improve specify dummy parser, fixes #1144 | Clifford Wolf | 2019-06-28 | 1 | -2/+9 |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | | | Merge pull request #1154 from whitequark/manual-sync-always | Clifford Wolf | 2019-07-03 | 1 | -2/+3 |
| |\ \ \ | | | | | | | | | manual: explain the purpose of `sync always` | ||||
| | * | | | manual: explain the purpose of `sync always`. | whitequark | 2019-07-02 | 1 | -2/+3 |
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| * | | | Merge pull request #1150 from YosysHQ/eddie/script_from_wire | Eddie Hung | 2019-07-02 | 3 | -8/+60 |
| |\ \ \ | |/ / |/| | | Add "script -select [selection]" to allow commands to be taken from wires | ||||
| | * | | Update test for Pass::call_on_module() | Eddie Hung | 2019-07-02 | 1 | -1/+1 |
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| | * | | Use Pass::call_on_module() as per @cliffordwolf comments | Eddie Hung | 2019-07-02 | 1 | -1/+1 |
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| | * | | Update test too | Eddie Hung | 2019-07-02 | 1 | -2/+2 |
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| | * | | script -select -> script -scriptwire | Eddie Hung | 2019-07-02 | 2 | -6/+6 |
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| | * | | Space | Eddie Hung | 2019-07-01 | 1 | -0/+1 |
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| | * | | Move CHANGELOG entry from yosys-0.8 to 0.9 | Eddie Hung | 2019-07-01 | 1 | -7/+1 |
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| | * | | Merge branch 'master' into eddie/script_from_wire | Eddie Hung | 2019-07-01 | 4 | -5/+15 |
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| | * \ \ | Merge branch 'master' into eddie/script_from_wire | Eddie Hung | 2019-06-28 | 1 | -1/+1 |
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| | * | | | | Try command in another module | Eddie Hung | 2019-06-28 | 1 | -0/+3 |
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| | * | | | | Add to CHANGELOG | Eddie Hung | 2019-06-28 | 1 | -0/+6 |
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| | * | | | | Support ability for "script -select" to take commands from wires | Eddie Hung | 2019-06-28 | 1 | -8/+39 |
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| | * | | | | Add test | Eddie Hung | 2019-06-28 | 1 | -0/+17 |
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| * | | | | | Merge pull request #1153 from YosysHQ/dave/fix_multi_mux | David Shah | 2019-07-02 | 3 | -3/+25 |
| |\ \ \ \ \ | | | | | | | | | | | | | memory_dff: Fix checking of feedback mux input when more than one mux | ||||
| | * | | | | | memory_dff: Fix checking of feedback mux input when more than one mux | David Shah | 2019-07-02 | 3 | -3/+25 |
| |/ / / / / | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
| * | | / / | Fix read_verilog assert/assume/etc on default case label, fixes ↵ | Clifford Wolf | 2019-07-02 | 1 | -0/+2 |
| | |_|/ / |/| | | | | | | | | | | | | | | | | | | | YosysHQ/SymbiYosys#53 Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | | | | Move abc9 from yosys-0.8 to yosys-0.9 in CHANGELOG | Eddie Hung | 2019-07-01 | 1 | -5/+11 |
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| * | | | | Merge branch 'master' of github.com:YosysHQ/yosys | Eddie Hung | 2019-07-01 | 3 | -0/+4 |
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| | * | | | install *_nowide.lut files | Eddie Hung | 2019-06-29 | 2 | -0/+3 |
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| | * | | | Merge pull request #1149 from gsomlo/gls-1098-abcext-fixup | Eddie Hung | 2019-06-28 | 1 | -0/+1 |
| | |\ \ \ | | |/ / | |/| | | Make abc9 pass aware of optional ABCEXTERNAL override | ||||
| | | * | | Make abc9 pass aware of optional ABCEXTERNAL override | Gabriel L. Somlo | 2019-06-28 | 1 | -0/+1 |
| | | | | | | | | | | | | | | | | | Signed-off-by: Gabriel Somlo <gsomlo@gmail.com> | ||||
| * | | | | autotest.sh to define _AUTOTB when test_autotb | Eddie Hung | 2019-06-28 | 1 | -1/+1 |
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| * | | | Replace log_assert() with meaningful log_error() | Eddie Hung | 2019-06-28 | 1 | -1/+5 |
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| * | | | Remove peepopt call in synth_xilinx since already in synth -run coarse | Eddie Hung | 2019-06-28 | 1 | -5/+0 |
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| * | | Add missing CHANGELOG entries | Eddie Hung | 2019-06-28 | 1 | -0/+3 |
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| * | | Fix spacing | Eddie Hung | 2019-06-28 | 1 | -2/+2 |
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| * | | Merge pull request #1098 from YosysHQ/xaig | Eddie Hung | 2019-06-28 | 45 | -247/+3642 |
| |\ \ | | | | | | | "abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs) | ||||
| | * | | Add generic __builtin_bswap32 function | Eddie Hung | 2019-06-28 | 1 | -0/+15 |
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| | * | | Also fix write_aiger for UB | Eddie Hung | 2019-06-28 | 1 | -26/+26 |
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| | * | | Fix more potential for undefined behaviour due to container invalidation | Eddie Hung | 2019-06-28 | 1 | -6/+10 |
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| | * | | Update synth_ice40 -device doc to be relevant for -abc9 only | Eddie Hung | 2019-06-28 | 1 | -2/+2 |
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| | * | | Disable boxing of ECP5 dist RAM due to regression | Eddie Hung | 2019-06-28 | 1 | -1/+1 |
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| | * | | Add write address to abc_scc_break of ECP5 dist RAM | Eddie Hung | 2019-06-28 | 1 | -1/+1 |
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| | * | | Fix DO4 typo | Eddie Hung | 2019-06-28 | 1 | -1/+1 |
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| | * | | Reduce diff with upstream | Eddie Hung | 2019-06-27 | 1 | -4/+2 |
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index : iCE40/yosys | |
| clone of https://github.com/YosysHQ/yosys |
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