| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Move tests/techmap/abc9 to simple_abc9 | Eddie Hung | 2019-02-20 | 4 | -23/+0 |
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| * | Add tests/simple_abc9 | Eddie Hung | 2019-02-20 | 1 | -0/+23 |
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| * | abc9 to cope with multiple modules | Eddie Hung | 2019-02-20 | 1 | -7/+11 |
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| * | abc9 to use & syntax for -fast, and name fixes | Eddie Hung | 2019-02-20 | 1 | -5/+5 |
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| * | read_aiger: new naming fixes | Eddie Hung | 2019-02-20 | 1 | -5/+5 |
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| * | read_aiger to name wires with internal name, less likely to clash | Eddie Hung | 2019-02-20 | 1 | -18/+15 |
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| * | write_xaiger to not write latches, CO/PO fixes | Eddie Hung | 2019-02-20 | 1 | -17/+26 |
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| * | synth to take -abc9 argument | Eddie Hung | 2019-02-20 | 1 | -5/+13 |
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| * | abc9 to cope with indexed wires when creating $lut from $_NOT_ | Eddie Hung | 2019-02-19 | 1 | -1/+6 |
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| * | Add a quick abc9 test | Eddie Hung | 2019-02-19 | 4 | -0/+29 |
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| * | Same for ascii AIGERs too | Eddie Hung | 2019-02-19 | 1 | -6/+13 |
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| * | read_aiger to cope with non-unique POs | Eddie Hung | 2019-02-19 | 1 | -6/+13 |
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| * | Merge branch 'master' into xaig | Eddie Hung | 2019-02-19 | 9 | -160/+353 |
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| | * | Merge pull request #805 from eddiehung/dff_init | Eddie Hung | 2019-02-19 | 4 | -2/+76 |
| | |\ | | | | | | | write_verilog to write initial statement for initial flop state | ||||
| | | * | Instead of INIT param on cells, use initial statement with hier ref as | Eddie Hung | 2019-02-17 | 1 | -18/+13 |
| | | | | | | | | | | | | | per @cliffordwolf | ||||
| | | * | Revert "Add INIT parameter to all ff/latch cells" | Eddie Hung | 2019-02-17 | 2 | -86/+43 |
| | | | | | | | | | | | | | This reverts commit 742b4e01b498ae2e735d40565f43607d69a015d8. | ||||
| | | * | Merge https://github.com/YosysHQ/yosys into dff_init | Eddie Hung | 2019-02-17 | 9 | -100/+345 |
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| | * | | Merge pull request #811 from ucb-bar/firrtlfixes | Clifford Wolf | 2019-02-17 | 6 | -56/+298 |
| | |\ \ | | | | | | | | | Update cells supported for verilog to FIRRTL conversion. | ||||
| | | * | | Removed unused variables, functions. | Jim Lawson | 2019-02-15 | 1 | -20/+0 |
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| | | * | | Append (instead of over-writing) EXTRA_FLAGS | Jim Lawson | 2019-02-15 | 1 | -1/+1 |
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| | | * | | Update cells supported for verilog to FIRRTL conversion. | Jim Lawson | 2019-02-15 | 5 | -55/+317 |
| | |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Issue warning messages for missing parameterized modules and attempts to set initial values. Replace simple "if (cell-type)" with "else if" chain. Fix FIRRTL shift handling. Add support for parameterized modules, $shift, $shiftx. Handle default output file. Deal with no top module. Automatically run pmuxtree pass. Allow EXTRA_FLAGS and SEED parameters to be set in the environment for tests/tools/autotest.mk. Support FIRRTL regression testing in tests/tools/autotest.sh Add xfirrtl files to test directories to exclude files from FIRRTL regression tests that are known to fail. | ||||
| * | | | abc9 to replace $_NOT_ with $lut | Eddie Hung | 2019-02-19 | 1 | -4/+39 |
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| * | | | read_aiger to create sane $lut names, and rename when renaming driving wire | Eddie Hung | 2019-02-19 | 1 | -2/+11 |
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| * | | | Add comment | Eddie Hung | 2019-02-19 | 1 | -1/+2 |
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| * | | | Get rid of boost dep, fix the FIXMEs for Win32? | Eddie Hung | 2019-02-19 | 1 | -14/+14 |
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| * | | | Get rid of debugging stuff in abc9 | Eddie Hung | 2019-02-16 | 1 | -6/+1 |
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| * | | | In read_xaiger, do not construct ConstEval for every LUT | Eddie Hung | 2019-02-16 | 1 | -1/+1 |
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| * | | | Cleanup | Eddie Hung | 2019-02-16 | 1 | -4/+5 |
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| * | | | read_aiger to ignore output = input of same wire; also create new output for ↵ | Eddie Hung | 2019-02-16 | 1 | -2/+16 |
| | | | | | | | | | | | | | different wire | ||||
| * | | | Cleanup | Eddie Hung | 2019-02-16 | 1 | -2/+1 |
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| * | | | write_xaiger to support non-bit cell connections, and cope with COs for -O | Eddie Hung | 2019-02-16 | 1 | -13/+15 |
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| * | | | abc9 to write_aiger with -O option, and ignore dummy outputs | Eddie Hung | 2019-02-16 | 1 | -2/+8 |
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| * | | | write_aiger -O to write dummy output as __dummy_o__ | Eddie Hung | 2019-02-16 | 1 | -2/+5 |
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| * | | | abc9 to handle comb loops, cope with constant outputs, disconnect using new wire | Eddie Hung | 2019-02-16 | 1 | -4/+67 |
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| * | | | read_aiger to disable log_debug | Eddie Hung | 2019-02-16 | 1 | -1/+2 |
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| * | | | expose command to not skip 'internal' wires beginning with '$' | Eddie Hung | 2019-02-16 | 1 | -1/+1 |
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| * | | | read_xaiger() to use f.read() not readsome() | Eddie Hung | 2019-02-16 | 1 | -1/+2 |
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| * | | | abc9 to cope with non-wideports, count cells properly | Eddie Hung | 2019-02-16 | 1 | -11/+54 |
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| * | | | Tidy up write_xaiger | Eddie Hung | 2019-02-16 | 1 | -8/+6 |
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| * | | | write_aiger() to perform CI/CO post-processing and fix symbols | Eddie Hung | 2019-02-16 | 1 | -7/+17 |
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| * | | | read_aiger() to cope with constant outputs, mixed wideports, do cleaning | Eddie Hung | 2019-02-16 | 1 | -8/+130 |
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| * | | | Move lookup inside if | Eddie Hung | 2019-02-15 | 1 | -2/+2 |
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| * | | | Fixes needed for DFF circuits | Eddie Hung | 2019-02-15 | 1 | -4/+3 |
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| * | | | Refactor | Eddie Hung | 2019-02-15 | 1 | -29/+32 |
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| * | | | Cope with width != 1 when re-mapping cells | Eddie Hung | 2019-02-15 | 1 | -11/+25 |
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| * | | | abc9 to stitch results with CI/CO properly | Eddie Hung | 2019-02-15 | 1 | -16/+32 |
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| * | | | read_aiger with more asserts, and call clean | Eddie Hung | 2019-02-15 | 1 | -4/+11 |
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| * | | | write_xaiger to cope with unknown cells by transforming them to CI/CO | Eddie Hung | 2019-02-15 | 1 | -6/+44 |
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| * | | | More cleanup | Eddie Hung | 2019-02-14 | 1 | -15/+6 |
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| * | | | More cleanup of write_xaiger | Eddie Hung | 2019-02-14 | 1 | -73/+1 |
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index : iCE40/yosys | |
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