| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Do not put constants into output_bits | Eddie Hung | 2019-04-16 | 1 | -2/+2 |
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| * | Remove write_verilog call | Eddie Hung | 2019-04-16 | 1 | -1/+1 |
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| * | Fix spacing | Eddie Hung | 2019-04-16 | 2 | -2/+2 |
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| * | Merge branch 'xaig' into xc7mux | Eddie Hung | 2019-04-16 | 2 | -3/+1 |
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| | * | Re-enable partsel.v test | Eddie Hung | 2019-04-16 | 1 | -1/+0 |
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| | * | abc9 to call "setundef -zero" behaving as for abc | Eddie Hung | 2019-04-16 | 1 | -0/+3 |
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| * | | NULL check before use | Eddie Hung | 2019-04-16 | 1 | -1/+1 |
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| * | | WIP for box support | Eddie Hung | 2019-04-16 | 1 | -36/+93 |
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| * | | ABC to read_box before reading netlist | Eddie Hung | 2019-04-16 | 1 | -1/+3 |
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| * | | Make cells.box whiteboxes not blackboxes | Eddie Hung | 2019-04-16 | 1 | -2/+2 |
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| * | | read_verilog cells_box.v before techmap | Eddie Hung | 2019-04-16 | 1 | -1/+1 |
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| * | | synth_xilinx: before abc read +/xilinx/cells_box.v | Eddie Hung | 2019-04-16 | 1 | -0/+1 |
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| * | | Add +/xilinx/cells_box.v containing models for ABC boxes | Eddie Hung | 2019-04-16 | 2 | -0/+11 |
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| * | | For 'stat' do not count modules with abc_box_id | Eddie Hung | 2019-04-16 | 1 | -0/+3 |
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| * | | Do not call abc on modules with abc_box_id attr | Eddie Hung | 2019-04-16 | 1 | -0/+3 |
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| * | | Revert "Add abc_box_id attribute to MUXF7/F8 cells" | Eddie Hung | 2019-04-16 | 1 | -2/+0 |
| | | | | | | | | | This reverts commit 8fbbd9b129697152c93c35831c1d50982702a3ec. | ||||
| * | | Use abc_box_id | Eddie Hung | 2019-04-15 | 1 | -2/+1 |
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| * | | Check abc_box_id attr | Eddie Hung | 2019-04-15 | 1 | -1/+16 |
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| * | | Add abc_box_id attribute to MUXF7/F8 cells | Eddie Hung | 2019-04-15 | 1 | -0/+2 |
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| * | | Merge branch 'xaig' into xc7mux | Eddie Hung | 2019-04-15 | 9 | -100/+246 |
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| | * | Merge remote-tracking branch 'origin/master' into xaig | Eddie Hung | 2019-04-15 | 3 | -6/+5 |
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| | | * | Merge pull request #937 from YosysHQ/revert-932-eddie/fixdlatch | Eddie Hung | 2019-04-15 | 2 | -4/+3 |
| | | |\ | | | | | | | | | Revert "Recognise default entry in case even if all cases covered (fix for #931)" | ||||
| | | | * | Revert "Recognise default entry in case even if all cases covered (fix for ↵ | Eddie Hung | 2019-04-15 | 2 | -4/+3 |
| | | |/ | | | | | | | | | | #931)" | ||||
| | | * | Merge pull request #936 from YosysHQ/README-fix-quotes | Eddie Hung | 2019-04-15 | 1 | -2/+2 |
| | | |\ | | | | | | | | | README: fix some incorrect quoting | ||||
| | | | * | README: fix some incorrect quoting. | whitequark | 2019-04-15 | 1 | -2/+2 |
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| | * | | Forgot backslashes | Eddie Hung | 2019-04-12 | 1 | -1/+1 |
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| | * | | Handle __dummy_o__ and __const[01]__ in read_aiger not abc | Eddie Hung | 2019-04-12 | 2 | -18/+8 |
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| | * | | abc to ignore __dummy_o__ and __const[01]__ when re-integrating | Eddie Hung | 2019-04-12 | 1 | -6/+20 |
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| | * | | Output __const0__ and __const1__ CIs | Eddie Hung | 2019-04-12 | 1 | -7/+10 |
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| | * | | Merge branch 'xaig' of github.com:YosysHQ/yosys into xaig | Eddie Hung | 2019-04-12 | 1 | -12/+32 |
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| | | * | | Fix inout handling for -map option | Eddie Hung | 2019-04-12 | 1 | -10/+30 |
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| | * | | | Merge branch 'xaig' of github.com:YosysHQ/yosys into xaig | Eddie Hung | 2019-04-12 | 0 | -0/+0 |
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| | | * | | Merge remote-tracking branch 'origin/master' into xaig | Eddie Hung | 2019-04-12 | 7 | -50/+76 |
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| | * | | | Use -map instead of -symbols for aiger | Eddie Hung | 2019-04-12 | 1 | -2/+3 |
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| | * | | | ci_bits and co_bits now a list, order is important for ABC | Eddie Hung | 2019-04-12 | 1 | -24/+34 |
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| | * | | | Also cope with duplicated CIs | Eddie Hung | 2019-04-12 | 1 | -5/+23 |
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| | * | | | WIP | Eddie Hung | 2019-04-12 | 1 | -14/+68 |
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| | * | | | Comment out | Eddie Hung | 2019-04-12 | 1 | -1/+1 |
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| | * | | | Add support for synth_xilinx -abc9 and ignore abc9 -dress opt | Eddie Hung | 2019-04-12 | 2 | -1/+14 |
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| | * | | | Cope with an output having same name as an input (i.e. CO) | Eddie Hung | 2019-04-12 | 1 | -5/+23 |
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| | * | | | Merge remote-tracking branch 'origin/master' into xaig | Eddie Hung | 2019-04-12 | 7 | -50/+76 |
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| | | * | Merge pull request #928 from litghost/add_xc7_sim_models | Eddie Hung | 2019-04-12 | 3 | -41/+60 |
| | | |\ | | | | | | | | | Add additional cells sim models for core 7-series primitives. | ||||
| | | | * | Remove BUFGCTRL, BUFHCE and LUT6_2 from cells_xtra. | Keith Rothman | 2019-04-12 | 3 | -52/+14 |
| | | | | | | | | | | | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> | ||||
| | | | * | Fix LUT6_2 definition. | Keith Rothman | 2019-04-09 | 1 | -3/+3 |
| | | | | | | | | | | | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> | ||||
| | | | * | Add additional cells sim models for core 7-series primatives. | Keith Rothman | 2019-04-09 | 1 | -0/+57 |
| | | | | | | | | | | | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> | ||||
| * | | | | PI before CI | Eddie Hung | 2019-04-12 | 1 | -2/+2 |
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| * | | | | Merge remote-tracking branch 'origin/master' into xc7mux | Eddie Hung | 2019-04-12 | 1 | -3/+9 |
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| | * | | | Merge pull request #933 from dh73/master | Clifford Wolf | 2019-04-12 | 1 | -3/+9 |
| | |\ \ \ | | | | | | | | | | | Fixing issues in CycloneV cell sim | ||||
| | | * | | | Fixing issues in CycloneV cell sim | Diego | 2019-04-11 | 1 | -3/+9 |
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| | * | | | Merge pull request #932 from YosysHQ/eddie/fixdlatch | Clifford Wolf | 2019-04-12 | 2 | -3/+4 |
| | |\ \ \ | | |/ / | |/| | | Recognise default entry in case even if all cases covered (fix for #931) | ||||
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index : iCE40/yosys | |
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