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| * | | | | | | | | | | | | | | | | Add "fmcombine -initeq -anyeq"Clifford Wolf2019-05-111-3/+38
| * | | | | | | | | | | | | | | | | Add "stat -tech xilinx"Clifford Wolf2019-05-112-4/+74
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| * | | | | | | | | | | | | | | | Merge pull request #1000 from bwidawsk/synth-formatClifford Wolf2019-05-092-222/+224
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| | * | | | | | | | | | | | | | | | Fix formatting for synth_intel.ccBen Widawsky2019-05-091-222/+211
| | * | | | | | | | | | | | | | | | Add a .clang-formatBen Widawsky2019-05-091-0/+13
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| * | | | | | | | | | | | | | | | Add $stop to documentationClifford Wolf2019-05-091-3/+4
| * | | | | | | | | | | | | | | | Remove added newline (by re-running minisat 00_UPDATE.sh)Clifford Wolf2019-05-081-1/+0
| * | | | | | | | | | | | | | | | Merge pull request #991 from kristofferkoch/gcc9-warningsClifford Wolf2019-05-085-5/+9
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| | * | | | | | | | | | | | | | | | Fix all warnings that occurred when compiling with gcc9Kristoffer Ellersgaard Koch2019-05-085-5/+9
| * | | | | | | | | | | | | | | | | Merge pull request #998 from mdaiter/get_bool_attribute_optsClifford Wolf2019-05-081-4/+8
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| | * | | | | | | | | | | | | | | | | Minor optimization to get_attribute_boolMatthew Daiter2019-05-071-4/+8
| * | | | | | | | | | | | | | | | | | Add test case from #997Clifford Wolf2019-05-071-0/+12
| * | | | | | | | | | | | | | | | | | Fix handling of partial init attributes in write_verilog, fixes #997Clifford Wolf2019-05-071-1/+2
| * | | | | | | | | | | | | | | | | | Merge pull request #996 from mdaiter/ceil_log2_optsClifford Wolf2019-05-072-3/+5
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| | * | | | | | | | | | | | | | | | | | Optimize ceil_log2 functionMatthew Daiter2019-05-072-3/+5
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| * | | | | | | | | | | | | | | | | | Add "synth_xilinx -arch"Clifford Wolf2019-05-071-1/+13
| * | | | | | | | | | | | | | | | | | More opt_clean cleanupsClifford Wolf2019-05-071-26/+36
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| * | | | | | | | | | | | | | | | | Merge pull request #946 from YosysHQ/clifford/specifyClifford Wolf2019-05-0619-51/+810
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| | * | | | | | | | | | | | | | | | | Improve tests/various/specify.ysClifford Wolf2019-05-061-2/+32
| | * | | | | | | | | | | | | | | | | Add "real" keyword to ilang formatClifford Wolf2019-05-063-2/+12
| | * | | | | | | | | | | | | | | | | Merge branch 'master' of github.com:YosysHQ/yosys into clifford/specifyClifford Wolf2019-05-063-12/+32
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| | * | | | | | | | | | | | | | | | | | Improve write_verilog specify supportClifford Wolf2019-05-043-16/+75
| | * | | | | | | | | | | | | | | | | | Update READMEClifford Wolf2019-05-041-5/+1
| | * | | | | | | | | | | | | | | | | | More testingEddie Hung2019-05-032-2/+5
| | * | | | | | | | | | | | | | | | | | Fix spacingEddie Hung2019-05-031-6/+6
| | * | | | | | | | | | | | | | | | | | Add quick-and-dirty specify testsEddie Hung2019-05-032-0/+53
| | * | | | | | | | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into clifford/specifyEddie Hung2019-05-0340-405/+931
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| | * | | | | | | | | | | | | | | | | | | Add specify support to READMEClifford Wolf2019-04-231-0/+5
| | * | | | | | | | | | | | | | | | | | | Improve $specrule interfaceClifford Wolf2019-04-234-13/+23
| | * | | | | | | | | | | | | | | | | | | Improve $specrule interfaceClifford Wolf2019-04-233-24/+24
| | * | | | | | | | | | | | | | | | | | | Add $specrule cells for $setup/$hold/$skew specify rulesClifford Wolf2019-04-239-6/+133
| | * | | | | | | | | | | | | | | | | | | Preserve $specify[23] cellsClifford Wolf2019-04-231-1/+1
| | * | | | | | | | | | | | | | | | | | | Allow $specify[23] cells in blackbox modulesClifford Wolf2019-04-231-0/+6
| | * | | | | | | | | | | | | | | | | | | Rename T_{RISE,FALL}_AVG to T_{RISE,FALL}_TYP to better match verilog std nom...Clifford Wolf2019-04-234-76/+76
| | * | | | | | | | | | | | | | | | | | | Add $specify2/$specify3 support to write_verilogClifford Wolf2019-04-231-0/+47
| | * | | | | | | | | | | | | | | | | | | Add support for $assert/$assume/$cover to write_verilogClifford Wolf2019-04-231-0/+10
| | * | | | | | | | | | | | | | | | | | | Add CellTypes support for $specify2 and $specify3Clifford Wolf2019-04-232-0/+7
| | * | | | | | | | | | | | | | | | | | | Add InternalCellChecker support for $specify2 and $specify3Clifford Wolf2019-04-231-7/+21
| | * | | | | | | | | | | | | | | | | | | Checking and fixing specify cells in genRTLILClifford Wolf2019-04-231-1/+15
| | * | | | | | | | | | | | | | | | | | | Un-break default specify parserClifford Wolf2019-04-231-0/+1
| | * | | | | | | | | | | | | | | | | | | Add specify parserClifford Wolf2019-04-235-33/+253
| | * | | | | | | | | | | | | | | | | | | Add $specify2 and $specify3 cells to simlibClifford Wolf2019-04-231-0/+147
| * | | | | | | | | | | | | | | | | | | | Merge pull request #975 from YosysHQ/clifford/fix968Clifford Wolf2019-05-063-13/+66
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| | * \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ Merge branch 'master' of github.com:YosysHQ/yosys into clifford/fix968Clifford Wolf2019-05-0635-290/+787
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| | * | | | | | | | | | | | | | | | | | | | | Further improve unused-detection for opt_clean driver-driver conflict warningClifford Wolf2019-05-031-5/+8
| | * | | | | | | | | | | | | | | | | | | | | Improve unused-detection for opt_clean driver-driver conflict warningClifford Wolf2019-05-031-21/+29
| | * | | | | | | | | | | | | | | | | | | | | Add additional test cases for for-loopsClifford Wolf2019-05-011-0/+25
| | * | | | | | | | | | | | | | | | | | | | | Silently resolve completely unused cell-vs-const driver-driver conflictsClifford Wolf2019-05-011-2/+21
| | * | | | | | | | | | | | | | | | | | | | | Re-enable "final loop assignment" featureClifford Wolf2019-05-011-2/+0
| * | | | | | | | | | | | | | | | | | | | | | Merge pull request #871 from YosysHQ/verific_importClifford Wolf2019-05-064-44/+181
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