| Commit message (Expand) | Author | Age | Files | Lines | ||
|---|---|---|---|---|---|---|
| ... | ||||||
| | * | | | write_verilog: dump zero width sigspecs correctly. | whitequark | 2021-12-11 | 1 | -1/+2 | |
| |/ / / | ||||||
| * | | | Bump version | github-actions[bot] | 2021-12-11 | 1 | -1/+1 | |
| * | | | Merge pull request #3102 from YosysHQ/claire/enumxz | Miodrag Milanović | 2021-12-10 | 1 | -1/+1 | |
| |\ \ \ | ||||||
| | * | | | Fix verific import of enum values with x and/or z | Claire Xenia Wolf | 2021-12-10 | 1 | -1/+1 | |
| * | | | | Merge pull request #3097 from YosysHQ/modport | Miodrag Milanović | 2021-12-10 | 1 | -2/+12 | |
| |\ \ \ \ | |/ / / |/| | | | ||||||
| | * | | | Update verific.cc | Claire Xen | 2021-12-10 | 1 | -4/+7 | |
| | * | | | If direction NONE use that from first bit | Miodrag Milanovic | 2021-12-08 | 1 | -0/+7 | |
| * | | | | Merge pull request #3099 from YosysHQ/claire/readargs | Claire Xen | 2021-12-10 | 9 | -41/+52 | |
| |\ \ \ \ | ||||||
| | * | | | | Fix the tests we just broke | Claire Xenia Wolf | 2021-12-10 | 6 | -10/+10 | |
| | * | | | | Added "yosys -r <topmodule>" | Claire Xenia Wolf | 2021-12-10 | 3 | -28/+35 | |
| | * | | | | Use "read" command to parse HDL files from Yosys command-line | Claire Xenia Wolf | 2021-12-09 | 1 | -4/+8 | |
| |/ / / / | ||||||
| * | | | | Bump version | github-actions[bot] | 2021-12-09 | 1 | -1/+1 | |
| * | | | | opt_mem_priority: Fix non-ascii char in help message. | Marcelina Kościelnicka | 2021-12-09 | 2 | -12/+2 | |
| |/ / / | ||||||
| * | | | Bump version | github-actions[bot] | 2021-12-04 | 1 | -1/+1 | |
| * | | | Next dev cycle | Miodrag Milanovic | 2021-12-03 | 2 | -2/+5 | |
| * | | | Release version 0.12 | Miodrag Milanovic | 2021-12-03 | 2 | -3/+3 | |
| * | | | Update manual | Miodrag Milanovic | 2021-12-03 | 1 | -22/+181 | |
| * | | | Add gitignore for gatemate | Miodrag Milanovic | 2021-12-03 | 1 | -0/+4 | |
| * | | | Make sure cell names are unique for wide operators | Miodrag Milanovic | 2021-12-03 | 1 | -2/+2 | |
| * | | | Bump version | github-actions[bot] | 2021-12-02 | 1 | -1/+1 | |
| * | | | Update CHANGELOG and CODEOWNERS | Miodrag Milanovic | 2021-12-01 | 2 | -0/+22 | |
| * | | | Bump version | github-actions[bot] | 2021-11-26 | 1 | -1/+1 | |
| * | | | intel_alm: preliminary Arria V support | Lofty | 2021-11-25 | 6 | -7/+199 | |
| * | | | sta: very crude static timing analysis pass | Lofty | 2021-11-25 | 9 | -62/+502 | |
| * | | | Bump version | github-actions[bot] | 2021-11-18 | 1 | -1/+1 | |
| * | | | Merge pull request #3080 from YosysHQ/micko/init_wire | Miodrag Milanović | 2021-11-17 | 1 | -4/+6 | |
| |\ \ \ | ||||||
| | * | | | Give initial wire unique ID, fixes #2914 | Miodrag Milanovic | 2021-11-17 | 1 | -4/+6 | |
| |/ / / | ||||||
| * | | | Bump version | github-actions[bot] | 2021-11-17 | 1 | -1/+1 | |
| * | | | Support parameters using struct as a wiretype (#3050) | Kamil Rakoczy | 2021-11-16 | 2 | -7/+74 | |
| * | | | Bump version | github-actions[bot] | 2021-11-14 | 1 | -1/+1 | |
| * | | | synth_gatemate Revert cascade A/B port mixup | Patrick Urban | 2021-11-13 | 2 | -12/+4 | |
| * | | | synth_gatemate: Remove iob_map invokation | Patrick Urban | 2021-11-13 | 1 | -1/+0 | |
| * | | | synth_gatemate: Add block RAM cascade support | Patrick Urban | 2021-11-13 | 2 | -112/+96 | |
| * | | | synth_gatemate: Remove obsolete iob_map | Patrick Urban | 2021-11-13 | 3 | -61/+2 | |
| * | | | synth_gatemate: Update pass | Patrick Urban | 2021-11-13 | 2 | -69/+33 | |
| * | | | synth_gatemate: Remove specify blocks | Patrick Urban | 2021-11-13 | 1 | -92/+0 | |
| * | | | synth_gatemate: Remove gatemate_bramopt pass | Patrick Urban | 2021-11-13 | 3 | -148/+0 | |
| * | | | synth_gatemate: Apply new test practice with assert-max | Patrick Urban | 2021-11-13 | 7 | -12/+12 | |
| * | | | synth_gatemate: Fix fsm test | Patrick Urban | 2021-11-13 | 1 | -2/+2 | |
| * | | | synth_gatemate: Revise block RAM read modes and initialization | Patrick Urban | 2021-11-13 | 3 | -71/+230 | |
| * | | | synth_gatemate: Remove unsupported FF initialization | Patrick Urban | 2021-11-13 | 1 | -2/+0 | |
| * | | | synth_gatemate: Rename multiplier factor parameters | Patrick Urban | 2021-11-13 | 1 | -13/+10 | |
| * | | | synth_gatemate: Registers are uninitialized | Patrick Urban | 2021-11-13 | 2 | -3/+3 | |
| * | | | Allow initial blocks to be disabled during tests | Patrick Urban | 2021-11-13 | 6 | -4/+20 | |
| * | | | synth_gatemate: Apply review remarks | Patrick Urban | 2021-11-13 | 6 | -279/+212 | |
| * | | | synth_gatemate: Apply review remarks | Patrick Urban | 2021-11-13 | 5 | -141/+86 | |
| * | | | synth_gatemate: Initial implementation | Patrick Urban | 2021-11-13 | 29 | -0/+4053 | |
| * | | | Bump version | github-actions[bot] | 2021-11-13 | 1 | -1/+1 | |
| * | | | show: Fix wire bit indexing. | Marcelina Kościelnicka | 2021-11-12 | 1 | -3/+16 | |
| * | | | update abc | Miodrag Milanovic | 2021-11-12 | 1 | -1/+1 | |
 |
index : iCE40/yosys | |
| [no description] |
| aboutsummaryrefslogtreecommitdiffstats |