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* Improve Verific importer blackbox handlingClifford Wolf2018-10-081-2/+14
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add "write_edif -attrprop"Clifford Wolf2018-10-081-11/+28
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix compiler warning in verific.ccClifford Wolf2018-10-081-0/+2
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix misspelling in issue_template.mdTim Ansell2018-10-081-1/+1
| | | It's been bugging me :-P
* Fix IdString M in setup_stdcells()Adrian Wheeldon2018-10-081-1/+1
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* Add inout ports to cells_xtra.vClifford Wolf2018-10-082-2/+14
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* xilinx: Adding missing inout IO port to IOBUFTim Ansell2018-10-081-0/+1
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* Fix for issue 594.Tom Verbeure2018-10-081-1/+2
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* Add read_verilog $changed supportDan Gisselquist2018-10-081-1/+4
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* ecp5: Don't map ROMs to DRAMDavid Shah2018-10-081-0/+1
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* Fix handling of $past 2nd argument in read_verilogClifford Wolf2018-10-081-1/+1
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Update to v2 YosysVS templateClifford Wolf2018-10-081-4/+4
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add "read_verilog -noassert -noassume -assert-assumes"Clifford Wolf2018-10-083-6/+49
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Added support for ommited "parameter" in Verilog-2001 style parameter decl ↵Clifford Wolf2018-10-081-3/+9
| | | | | | in SV mode Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Update CHANGELOGClifford Wolf2018-10-081-2/+35
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* added prefix to FDirection constants, fixing windows buildMiodrag Milanovic2018-10-081-11/+11
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* Update CHANGLELOGClifford Wolf2018-10-081-5/+27
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Update ChangelogClifford Wolf2018-10-081-1/+54
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix Cygwin build and document needed packagesMiodrag Milanovic2018-10-083-1/+14
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* Fixed typo in "verilog_write" help messageacw12512018-10-082-5/+5
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* Merge remote-tracking branch 'upstream/master'Jim Lawson2018-09-1711-14/+78
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| * Merge pull request #625 from aman-goel/masterClifford Wolf2018-09-141-1/+7
| |\ | | | | | | Minor revision to -expose in setundef pass
| | * Minor revision to -expose in setundef passAman Goel2018-09-101-1/+7
| | | | | | | | | | | | Adds default value option as -undef when -expose used. Not having set the value mode set can cause the setundef pass to abort.
| * | Merge pull request #627 from acw1251/masterClifford Wolf2018-09-141-1/+1
| |\ \ | | | | | | | | Fixed minor typo in "sim" help message
| | * | Fixed minor typo in "sim" help messageacw12512018-09-121-1/+1
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| * | Add iCE40 SB_SPRAM256KA simulation modelClifford Wolf2018-09-101-9/+30
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Add $lut support to Verilog back-endClifford Wolf2018-09-061-0/+13
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Add "verific -L <int>" optionClifford Wolf2018-09-043-2/+16
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Add "make ystests"Clifford Wolf2018-08-303-0/+10
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Add GCC to osx deps (#620)Miodrag Milanović2018-08-281-1/+1
| | | | | | | | | | | | | | | | | | * Add GCC to osx deps * Force gcc-7 install
* | | Merge pull request #4 from YosysHQ/masterJim Lawson2018-08-283-23/+112
|\| | | | | | | | merge with YosysHQ master
| * | Merge pull request #619 from mmicko/masterClifford Wolf2018-08-282-6/+0
| |\ \ | | | | | | | | Remove mercurial, since it is not needed anymore
| | * | Remove mercurial, since it is not needed anymoreMiodrag Milanovic2018-08-282-6/+0
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| * | Merge pull request #618 from ucb-bar/firrtl+modules+shiftfixesClifford Wolf2018-08-281-17/+112
| |\ \ | | | | | | | | Add support for modules.
| | * \ Merge branch 'master' into firrtl+modules+shiftfixesJim Lawson2018-08-2712-39/+92
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* | | | Merge pull request #3 from YosysHQ/masterJim Lawson2018-08-2712-39/+92
|\| | | | | | | | | | | merge with YosysHQ
| * | | Add "make coverage"Clifford Wolf2018-08-278-13/+21
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | Add ENABLE_GCOV build optionClifford Wolf2018-08-271-0/+11
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | Merge pull request #617 from mmicko/masterClifford Wolf2018-08-251-1/+1
| |\ \ \ | | | | | | | | | | static link flag on main executable
| | * | | static link flag on main executableMiodrag Milanovic2018-08-251-1/+1
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| * | | Merge pull request #610 from udif/udif_specify_round2Clifford Wolf2018-08-231-16/+39
| |\ \ \ | | | | | | | | | | More specify/endspecify fixes
| | * | | Fixed all known specify/endspecify issues, without breaking 'make test'.Udi Finkelstein2018-08-201-12/+12
| | | | | | | | | | | | | | | | | | | | | | | | | Some the of parser fixes may look strange but they were needed to avoid shift/reduce conflicts, due to the explicit parentheses in path_delay_value, and the mintypmax values without parentheses
| | * | | Yosys can now parse ↵Udi Finkelstein2018-08-201-10/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://github.com/verilog-to-routing/vtr-verilog-to-routing/blob/master/vtr_flow/primitives.v , (specify block ignored). Must use 'read_verilog -defer' due to a parameter not assigned a default value.
| | * | | A few minor enhancements to specify block parsing.Udi Finkelstein2018-08-151-2/+13
| | | | | | | | | | | | | | | | | | | | Just remember specify blocks are parsed but ignored.
| * | | | Merge pull request #614 from udif/pr_disable_dump_ptrClifford Wolf2018-08-233-9/+20
| |\ \ \ \ | | | | | | | | | | | | Added -no_dump_ptr flag for AST dump options in 'read_verilog'
| | * | | | Added -no_dump_ptr flag for AST dump options in 'read_verilog'Udi Finkelstein2018-08-233-9/+20
| |/ / / / | | | | | | | | | | | | | | | | | | | | | | | | | This option disables the memory pointer display. This is useful when diff'ing different dumps because otherwise the node pointers makes every diff line different when the AST content is the same.
| | | * | Remove unused functions.Jim Lawson2018-08-271-10/+0
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| | | * | Add support for module instances.Jim Lawson2018-08-231-17/+122
| |_|/ / |/| | | | | | | | | | | | | | | | | | | | | | | Don't pad logical operands to one bit. Use operand width and signedness in $reduce_bool. Shift amounts are unsigned and shouldn't be padded. Group "is invalid" with the wire declaration, not its use (otherwise it is incorrectly wired to 0).
* | | | Merge pull request #1 from YosysHQ/masterJim Lawson2018-08-22196-770/+2533
|\| | | | | | | | | | | merge with YosysHQ master
| * | | Add "verific -work" help messageClifford Wolf2018-08-221-0/+7
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
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