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* Add +/xilinx/cells_box.v containing models for ABC boxesEddie Hung2019-04-162-0/+11
* For 'stat' do not count modules with abc_box_idEddie Hung2019-04-161-0/+3
* Do not call abc on modules with abc_box_id attrEddie Hung2019-04-161-0/+3
* Revert "Add abc_box_id attribute to MUXF7/F8 cells"Eddie Hung2019-04-161-2/+0
* Use abc_box_idEddie Hung2019-04-151-2/+1
* Check abc_box_id attrEddie Hung2019-04-151-1/+16
* Add abc_box_id attribute to MUXF7/F8 cellsEddie Hung2019-04-151-0/+2
* Merge branch 'xaig' into xc7muxEddie Hung2019-04-159-100/+246
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| * Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-04-153-6/+5
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| | * Merge pull request #937 from YosysHQ/revert-932-eddie/fixdlatchEddie Hung2019-04-152-4/+3
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| | | * Revert "Recognise default entry in case even if all cases covered (fix for #9...Eddie Hung2019-04-152-4/+3
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| | * Merge pull request #936 from YosysHQ/README-fix-quotesEddie Hung2019-04-151-2/+2
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| | | * README: fix some incorrect quoting.whitequark2019-04-151-2/+2
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| * | Forgot backslashesEddie Hung2019-04-121-1/+1
| * | Handle __dummy_o__ and __const[01]__ in read_aiger not abcEddie Hung2019-04-122-18/+8
| * | abc to ignore __dummy_o__ and __const[01]__ when re-integratingEddie Hung2019-04-121-6/+20
| * | Output __const0__ and __const1__ CIsEddie Hung2019-04-121-7/+10
| * | Merge branch 'xaig' of github.com:YosysHQ/yosys into xaigEddie Hung2019-04-121-12/+32
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| | * | Fix inout handling for -map optionEddie Hung2019-04-121-10/+30
| * | | Merge branch 'xaig' of github.com:YosysHQ/yosys into xaigEddie Hung2019-04-120-0/+0
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| | * | Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-04-127-50/+76
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| * | | Use -map instead of -symbols for aigerEddie Hung2019-04-121-2/+3
| * | | ci_bits and co_bits now a list, order is important for ABCEddie Hung2019-04-121-24/+34
| * | | Also cope with duplicated CIsEddie Hung2019-04-121-5/+23
| * | | WIPEddie Hung2019-04-121-14/+68
| * | | Comment outEddie Hung2019-04-121-1/+1
| * | | Add support for synth_xilinx -abc9 and ignore abc9 -dress optEddie Hung2019-04-122-1/+14
| * | | Cope with an output having same name as an input (i.e. CO)Eddie Hung2019-04-121-5/+23
| * | | Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-04-127-50/+76
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| | * Merge pull request #928 from litghost/add_xc7_sim_modelsEddie Hung2019-04-123-41/+60
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| | | * Remove BUFGCTRL, BUFHCE and LUT6_2 from cells_xtra.Keith Rothman2019-04-123-52/+14
| | | * Fix LUT6_2 definition.Keith Rothman2019-04-091-3/+3
| | | * Add additional cells sim models for core 7-series primatives.Keith Rothman2019-04-091-0/+57
* | | | PI before CIEddie Hung2019-04-121-2/+2
* | | | Merge remote-tracking branch 'origin/master' into xc7muxEddie Hung2019-04-121-3/+9
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| * | | Merge pull request #933 from dh73/masterClifford Wolf2019-04-121-3/+9
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| | * | | Fixing issues in CycloneV cell simDiego2019-04-111-3/+9
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| * | | Merge pull request #932 from YosysHQ/eddie/fixdlatchClifford Wolf2019-04-122-3/+4
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* | | | Merge remote-tracking branch 'origin/pmux2shiftx' into xc7muxEddie Hung2019-04-111-1/+0
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| * | | | More unusedEddie Hung2019-04-111-1/+0
* | | | | Merge remote-tracking branch 'origin/pmux2shiftx' into xc7muxEddie Hung2019-04-116-8/+93
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| * | | | Remove unusedEddie Hung2019-04-111-1/+0
| * | | | FixesEddie Hung2019-04-111-20/+16
| * | | | WIPEddie Hung2019-04-112-0/+89
| * | | | Spelling fixesEddie Hung2019-04-111-2/+2
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| * | | Add default entry to testcaseEddie Hung2019-04-111-2/+3
| * | | Recognise default entry in case even if all cases covered (#931)Eddie Hung2019-04-111-1/+1
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| * | Fix a few typosEddie Hung2019-04-081-3/+3
* | | Fix cells_map.v some moreEddie Hung2019-04-111-7/+7
* | | More fine tuningEddie Hung2019-04-111-2/+2