aboutsummaryrefslogtreecommitdiffstats
Commit message (Collapse)AuthorAgeFilesLines
...
| * | Add timing constraints to osu035 exampleClifford Wolf2017-10-103-2/+4
| | |
| * | Remove some dead codeClifford Wolf2017-10-101-15/+0
| | |
| * | Allow $past, $stable, $rose, $fell in $global_clock blocksClifford Wolf2017-10-101-1/+5
| |/
| * Add $shiftx support to verilog front-endClifford Wolf2017-10-071-0/+17
| |
| * Update ABC to hg rev 0fc1803a77c0Clifford Wolf2017-10-061-1/+1
| |
| * Clean whitespace and permissions in techlibs/intelLarry Doolittle2017-10-0521-190/+190
| |
* | Start work on pre-processor for Verific SVA propertiesClifford Wolf2017-10-101-10/+153
|/
* Improve handling of Verific errorsClifford Wolf2017-10-051-11/+9
|
* Improve Verific error handling, check VHDL static assertsClifford Wolf2017-10-041-11/+25
|
* Add blackbox commandClifford Wolf2017-10-042-0/+82
|
* Fix nasty bug in Verific bindingsClifford Wolf2017-10-041-1/+1
|
* Merge branch 'pr_ast_const_funcs' of https://github.com/udif/yosysClifford Wolf2017-10-032-14/+14
|\
| * Turned a few member functions into const, esp. dumpAst(), dumpVlog().Udi Finkelstein2017-09-302-14/+14
| |
* | Merge branch 'fix_shift_reduce_conflict' of https://github.com/udif/yosysClifford Wolf2017-10-031-3/+5
|\ \
| * | Resolved classical Bison IF/THEN/ELSE shift/reduce conflict using the ↵Udi Finkelstein2017-09-301-3/+5
| |/ | | | | | | | | | | textbook solution (Oreilly 'Flex & Bison' page 189)
* | Merge branch 'dh73-master'Clifford Wolf2017-10-0331-729/+2965
|\ \ | |/ |/|
| * Rename "write_verilog -nobasenradix" to "write_verilog -decimal"Clifford Wolf2017-10-032-20/+14
| |
| * Tested and working altsyncarm without init filesdh732017-10-012-57/+59
| |
| * Fixed wrong declaration in Verilog backenddh732017-10-011-3/+3
| |
| * Adding Cyclone IV (E, GX), Arria 10, Cyclone V and LPM functions (ALTPLL and ↵dh732017-10-0131-730/+2970
|/ | | | M9K); M9K is not finished yet. Achronix Speedster also in this commit. Both Arria10 and Speedster-i are still experimental due complexity, but you can experiment around those devices right now
* Add first draft of eASIC back-endClifford Wolf2017-09-292-0/+191
|
* Fix synth_ice40 doc regarding -top defaultClifford Wolf2017-09-291-1/+1
|
* Allow $size and $bits in verilog mode, actually check test caseClifford Wolf2017-09-293-1/+3
|
* Merge pull request #425 from udif/udif_dollar_bitsClifford Wolf2017-09-292-1/+103
|\ | | | | Add $bits() and $size()
| * $size() now works correctly for all cases!Udi Finkelstein2017-09-262-22/+28
| | | | | | | | It seems the issues was that AST_MULTIRANGE is converted into a multirange_dimensions[] array on the AST_MEMORY node directly.
| * $size() seems to work now with or without the optional parameter.Udi Finkelstein2017-09-262-18/+58
| | | | | | | | Multidimensional arrays still don't work. I suspect the problem is that the array is flattened into a 1D array before $size() is evaluated.
| * enable $bits() and $size() functions only when the SystemVerilog flag is ↵Udi Finkelstein2017-09-261-1/+1
| | | | | | | | enabled for read_verilog
| * Added $bits() for memories as well.Udi Finkelstein2017-09-262-8/+31
| |
| * $size() now works with memories as well!Udi Finkelstein2017-09-262-3/+7
| |
| * Add $size() function. At the moment it works only on expressions, not on ↵Udi Finkelstein2017-09-262-0/+29
|/ | | | memories.
* Merge pull request #421 from stephengroat/osx-travisClifford Wolf2017-09-283-2/+12
|\ | | | | Add osx tests using brew bundle
| * delete bad backslashStephen2017-09-271-1/+1
| |
| * forgot to install bundlesStephen2017-09-271-0/+1
| |
| * Add osx tests using brew bundleStephen Groat2017-09-273-2/+11
|/
* Increase maximum LUT size in blifparse to 12 bitsClifford Wolf2017-09-271-1/+1
|
* Parse reals as string in JSON front-endClifford Wolf2017-09-261-0/+28
|
* Merge branch 'vlogpp-inc-fixes'Clifford Wolf2017-09-261-41/+69
|\
| * Minor coding style fixClifford Wolf2017-09-261-1/+1
| |
| * Merge branch 'master' of https://github.com/combinatorylogic/yosys into ↵Clifford Wolf2017-09-261-41/+69
|/| | | | | | | combinatorylogic-master
| * Adding support for string macros and macros with arguments after includecombinatorylogic2017-09-211-41/+69
| |
* | Fix ignoring of simulation timings so that invalid module parameters cause ↵Clifford Wolf2017-09-262-4/+2
|/ | | | syntax errors
* Merge pull request #413 from azonenberg/extract-reduce-tweaksClifford Wolf2017-09-161-86/+170
|\ | | | | Added support for off-chain loads in extract_reduce
| * Added missing "break"Andrew Zonenberg2017-09-151-0/+1
| |
| * Implemented off-chain support for extract_reduceAndrew Zonenberg2017-09-151-84/+157
| |
| * extract_reduce now only removes the head of the chain, relying on "clean" to ↵Andrew Zonenberg2017-09-151-9/+19
|/ | | | delete upstream cells. Added "-allow-off-chain" flag, but it's currently ignored.
* Merge branch 'master' of github.com:cliffordwolf/yosysClifford Wolf2017-09-151-2/+2
|\
| * Merge pull request #412 from azonenberg/reduce-fixesClifford Wolf2017-09-141-2/+2
| |\ | | | | | | extract_reduce: Fix segfault on "undriven" inputs
| | * extract_reduce: Fix segfault on "undriven" inputsRobert Ou2017-09-141-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | This is easily triggered when un-techmapping if the technology-specific cell library isn't loaded. Outputs of technology-specific cells will be seen as inputs, and nets using those outputs will be seen as undriven. Just ignore these cells because they can't be part of a reduce chain anyways.
* | | Update ABC to hg rev cd6984ee82d4Clifford Wolf2017-09-151-2/+2
|/ /
* | Merge pull request #411 from azonenberg/counter-extraction-fixesClifford Wolf2017-09-143-68/+183
|\ \ | | | | | | Various improvements and bug fixes to extract_counter
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-09 15:38:40 +0000