iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Fixed Verilog parser fix and more similar improvements	Clifford Wolf	2016-03-15	1	-18/+9
*	Use left-recursive rule for cell_port_list in Verilog parser.	Andrew Becker	2016-03-15	1	-6/+10
*	Bugfix in write_verilog for RTLIL processes	Clifford Wolf	2016-03-14	1	-9/+20
*	Cleanups and improvements in examples/cmos/	Clifford Wolf	2016-03-11	5	-12/+19
*	Merge commit 'b34385ec924b6067c1f82bdbae923f8062518956'	Clifford Wolf	2016-03-11	5	-9/+76
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\| *	Completed ngspice digital example with verilog tb	Uros Platise	2016-03-05	5	-9/+76
* \|	Fixed typos in verilog_defaults help message	Clifford Wolf	2016-03-10	1	-3/+3
* \|	Added "write_edif -nogndvcc"	Clifford Wolf	2016-03-08	1	-17/+34
* \|	Added examples/cxx-api/evaldemo.cc	Clifford Wolf	2016-03-08	1	-0/+55
* \|	Merge branch 'master' of github.com:cliffordwolf/yosys	Clifford Wolf	2016-03-07	7	-25/+123
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\| *	Added digital (xspice) example code to examples/cmos/	Clifford Wolf	2016-03-02	4	-1/+70
\| *	Be more conservative with net names in spice output	Clifford Wolf	2016-03-02	1	-18/+47
\| *	Merge pull request #119 from SebKuzminsky/spelling-fixes	Clifford Wolf	2016-02-29	2	-6/+6
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\| \| *	user-facing spelling fixes	Sebastian Kuzminsky	2016-02-28	2	-6/+6
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* /	Using "mfs" and "lutpack" in ABC lut mapping	Clifford Wolf	2016-03-07	1	-5/+14
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*	We are now in 0.6+ development	Clifford Wolf	2016-02-26	1	-1/+1
*	Yosys 0.6	Clifford Wolf	2016-02-26	1	-1/+1
*	Fixed BLIF parser for empty port assignments	Clifford Wolf	2016-02-24	1	-2/+2
*	Use easyer-to-read unoptimized ceil_log2()	Clifford Wolf	2016-02-15	1	-18/+5
*	Updated ABC to ae7d65e71adc	Clifford Wolf	2016-02-15	1	-1/+1
*	Updated command reference in manual	Clifford Wolf	2016-02-14	3	-16/+364
*	Changelog for upcoming 0.6 release	Clifford Wolf	2016-02-14	1	-0/+88
*	Fixed more visual studio warnings	Clifford Wolf	2016-02-14	1	-5/+3
*	Fixed some visual studio warnings	Clifford Wolf	2016-02-13	8	-10/+10
*	Merge branch 'master' of github.com:cliffordwolf/yosys	Clifford Wolf	2016-02-13	1	-1/+1
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\| *	Fixed MXE ABC build	Clifford Wolf	2016-02-13	1	-1/+1
* \|	Added "int ceil_log2(int)" function	Clifford Wolf	2016-02-13	5	-10/+58
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*	Run dffsr2dff in synth_xilinx	Clifford Wolf	2016-02-13	1	-0/+2
*	Support for more Verific primitives (patch I got per email)	Clifford Wolf	2016-02-13	1	-1/+31
*	Updated ABC	Clifford Wolf	2016-02-08	1	-1/+1
*	Work around DDR dout sim glitches in ice40 SB_IO sim model	Clifford Wolf	2016-02-07	1	-1/+7
*	Updated ABC	Clifford Wolf	2016-02-07	1	-1/+1
*	Added "stat -liberty" for calculating chip area	Clifford Wolf	2016-02-04	1	-6/+60
*	Bugfix in Verific front-end	Clifford Wolf	2016-02-03	1	-2/+5
*	Updated verific build instructions	Clifford Wolf	2016-02-02	1	-2/+0
*	Improved dffsr2dff pass	Clifford Wolf	2016-02-02	1	-5/+50
*	Added dffsr2dff	Clifford Wolf	2016-02-02	3	-0/+171
*	Added addBufGate module method	Clifford Wolf	2016-02-02	3	-0/+8
*	Use alphanumerical order instead of idstring idx in opt_clean compare_signals()	Clifford Wolf	2016-02-02	1	-1/+1
*	Added CodeOfConduct	Clifford Wolf	2016-02-01	1	-0/+73
*	Updated ABC to hg rev ee212a9e94df	Clifford Wolf	2016-02-01	1	-1/+1
*	Progress in cell library documentation	Clifford Wolf	2016-02-01	1	-0/+238
*	Added "abc -luts" option, Improved Xilinx logic mapping	Clifford Wolf	2016-02-01	2	-15/+39
*	Improvements in dfflibmap (FFs with Q/QN outputs, DFFs from ADFFs)	Clifford Wolf	2016-02-01	1	-8/+68
*	SigMap performance improvement	Clifford Wolf	2016-02-01	1	-1/+7
*	hashlib mfp<> performance improvements	Clifford Wolf	2016-02-01	1	-2/+7
*	Added reserve() method to haslib classes and	Clifford Wolf	2016-01-31	1	-2/+6
*	Merge branch 'rtlil_remove2_speedup' of https://github.com/kc8apf/yosys	Clifford Wolf	2016-01-31	2	-14/+88
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\| *	rtlil: Improve performance of SigSpec::extract(SigSpec, SigSpec*)	Rick Altherr	2016-01-31	1	-2/+31
\| *	rtlil: speed up SigSpec::sort_and_unify()	Rick Altherr	2016-01-31	1	-1/+11