iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	Merge commit 'b34385ec924b6067c1f82bdbae923f8062518956'	Clifford Wolf	2016-03-11	5	-9/+76
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\| *	Completed ngspice digital example with verilog tb	Uros Platise	2016-03-05	5	-9/+76
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* \|	Fixed typos in verilog_defaults help message	Clifford Wolf	2016-03-10	1	-3/+3
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* \|	Added "write_edif -nogndvcc"	Clifford Wolf	2016-03-08	1	-17/+34
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* \|	Added examples/cxx-api/evaldemo.cc	Clifford Wolf	2016-03-08	1	-0/+55
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* \|	Merge branch 'master' of github.com:cliffordwolf/yosys	Clifford Wolf	2016-03-07	7	-25/+123
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\| *	Added digital (xspice) example code to examples/cmos/	Clifford Wolf	2016-03-02	4	-1/+70
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\| *	Be more conservative with net names in spice output	Clifford Wolf	2016-03-02	1	-18/+47
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\| *	Merge pull request #119 from SebKuzminsky/spelling-fixes	Clifford Wolf	2016-02-29	2	-6/+6
\| \|\ \| \| \| \| \| \|	user-facing spelling fixes
\| \| *	user-facing spelling fixes	Sebastian Kuzminsky	2016-02-28	2	-6/+6
\| \|/ \| \| \| \| \| \| \| \|	"speciefied" -> "specified" "unkown" -> "unknown"
* /	Using "mfs" and "lutpack" in ABC lut mapping	Clifford Wolf	2016-03-07	1	-5/+14
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*	We are now in 0.6+ development	Clifford Wolf	2016-02-26	1	-1/+1
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*	Yosys 0.6	Clifford Wolf	2016-02-26	1	-1/+1
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*	Fixed BLIF parser for empty port assignments	Clifford Wolf	2016-02-24	1	-2/+2
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*	Use easyer-to-read unoptimized ceil_log2()	Clifford Wolf	2016-02-15	1	-18/+5
\| \| \| \| \|	see here for details on the optimized version: http://svn.clifford.at/handicraft/2016/esbmc/ceilog2.c
*	Updated ABC to ae7d65e71adc	Clifford Wolf	2016-02-15	1	-1/+1
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*	Updated command reference in manual	Clifford Wolf	2016-02-14	3	-16/+364
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*	Changelog for upcoming 0.6 release	Clifford Wolf	2016-02-14	1	-0/+88
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*	Fixed more visual studio warnings	Clifford Wolf	2016-02-14	1	-5/+3
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*	Fixed some visual studio warnings	Clifford Wolf	2016-02-13	8	-10/+10
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*	Merge branch 'master' of github.com:cliffordwolf/yosys	Clifford Wolf	2016-02-13	1	-1/+1
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\| *	Fixed MXE ABC build	Clifford Wolf	2016-02-13	1	-1/+1
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* \|	Added "int ceil_log2(int)" function	Clifford Wolf	2016-02-13	5	-10/+58
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*	Run dffsr2dff in synth_xilinx	Clifford Wolf	2016-02-13	1	-0/+2
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*	Support for more Verific primitives (patch I got per email)	Clifford Wolf	2016-02-13	1	-1/+31
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*	Updated ABC	Clifford Wolf	2016-02-08	1	-1/+1
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*	Work around DDR dout sim glitches in ice40 SB_IO sim model	Clifford Wolf	2016-02-07	1	-1/+7
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*	Updated ABC	Clifford Wolf	2016-02-07	1	-1/+1
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*	Added "stat -liberty" for calculating chip area	Clifford Wolf	2016-02-04	1	-6/+60
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*	Bugfix in Verific front-end	Clifford Wolf	2016-02-03	1	-2/+5
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*	Updated verific build instructions	Clifford Wolf	2016-02-02	1	-2/+0
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*	Improved dffsr2dff pass	Clifford Wolf	2016-02-02	1	-5/+50
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*	Added dffsr2dff	Clifford Wolf	2016-02-02	3	-0/+171
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*	Added addBufGate module method	Clifford Wolf	2016-02-02	3	-0/+8
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*	Use alphanumerical order instead of idstring idx in opt_clean compare_signals()	Clifford Wolf	2016-02-02	1	-1/+1
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*	Added CodeOfConduct	Clifford Wolf	2016-02-01	1	-0/+73
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*	Updated ABC to hg rev ee212a9e94df	Clifford Wolf	2016-02-01	1	-1/+1
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*	Progress in cell library documentation	Clifford Wolf	2016-02-01	1	-0/+238
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*	Added "abc -luts" option, Improved Xilinx logic mapping	Clifford Wolf	2016-02-01	2	-15/+39
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*	Improvements in dfflibmap (FFs with Q/QN outputs, DFFs from ADFFs)	Clifford Wolf	2016-02-01	1	-8/+68
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*	SigMap performance improvement	Clifford Wolf	2016-02-01	1	-1/+7
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*	hashlib mfp<> performance improvements	Clifford Wolf	2016-02-01	1	-2/+7
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*	Added reserve() method to haslib classes and	Clifford Wolf	2016-01-31	1	-2/+6
\| \| \| \|	calculate hashtable size based on entries capacity, not size
*	Merge branch 'rtlil_remove2_speedup' of https://github.com/kc8apf/yosys	Clifford Wolf	2016-01-31	2	-14/+88
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\| *	rtlil: Improve performance of SigSpec::extract(SigSpec, SigSpec*)	Rick Altherr	2016-01-31	1	-2/+31
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Converting to a pool<SigBit> is fairly expensive due to inserts somewhat frequently causing rehashing. Instead, walk through the pattern SigSpec directly on a chunk-by-chunk basis and apply it to this SigSpec's individual bits. Using chunks for the pattern minimizes the number of iterations in the outer loop.
\| *	rtlil: speed up SigSpec::sort_and_unify()	Rick Altherr	2016-01-31	1	-1/+11
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	std::set<> internally is often a red-black tree which is fairly expensive to create but fast to lookup. In the case of sort_and_unify(), a set<> is constructed as a temporary object to attempt to speed up lookups. Being a temporarily, however, the cost of creation far outweights the lookup improvement and is a net performance loss. Instead, sort the vector<> that already exists and then apply std::unique().
\| *	rtlil: improve performance of SigSpec::replace(SigSpec, SigSpec, SigSpec*)	Rick Altherr	2016-01-31	1	-6/+14
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\| *	genrtlil: avoid converting SigSpec to set<SigBit> when going through ↵	Rick Altherr	2016-01-31	1	-3/+3
\| \| \| \| \| \| \| \|	removeSignalFromCaseTree()
\| *	rtlil: improve performance of SigSpec::remove2(SigSpec, SigSpec*)	Rick Altherr	2016-01-31	1	-2/+29
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* \|	More clang sanitizer stuff	Clifford Wolf	2016-01-31	2	-3/+12
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