| Commit message (Expand) | Author | Age | Files | Lines | ||
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| | * | | | | | | | | | | | | Revert "Add -B option to autotest.sh to append to backend_opts" | Eddie Hung | 2019-02-21 | 1 | -4/+2 | |
| * | | | | | | | | | | | | | Merge pull request #817 from eddiehung/dff_init | Eddie Hung | 2019-02-20 | 1 | -21/+0 | |
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| | * | | | | | | | | | | | | Remove simple_defparam tests | Eddie Hung | 2019-02-20 | 1 | -21/+0 | |
| | | | | | | | * | | | | | | Add author name | Eddie Hung | 2019-03-19 | 1 | -0/+1 | |
| | | | | | | | * | | | | | | Add aiger tests to make tests | Eddie Hung | 2019-02-19 | 1 | -0/+1 | |
| | | | | | | | * | | | | | | Merge branch 'master' into read_aiger | Eddie Hung | 2019-02-19 | 0 | -0/+0 | |
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| * | | | | | | | | | | | | | Merge pull request #805 from eddiehung/dff_init | Eddie Hung | 2019-02-19 | 4 | -2/+76 | |
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| | | | | | | * | | | | | | Fix for using POSIX basename | Eddie Hung | 2019-02-19 | 1 | -2/+4 | |
| | | | | | | * | | | | | | Missing OSX headers? | Eddie Hung | 2019-02-17 | 1 | -0/+5 | |
| | | | | | | * | | | | | | Revert "Missing headers for Xcode?" | Eddie Hung | 2019-02-17 | 1 | -2/+0 | |
| | | | | | | * | | | | | | Merge branch 'dff_init' into read_aiger | Eddie Hung | 2019-02-17 | 3 | -104/+56 | |
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| | * | | | | | | | | | | | Instead of INIT param on cells, use initial statement with hier ref as | Eddie Hung | 2019-02-17 | 1 | -18/+13 | |
| | * | | | | | | | | | | | Revert "Add INIT parameter to all ff/latch cells" | Eddie Hung | 2019-02-17 | 2 | -86/+43 | |
| | | | | | | * | | | | | | read_aiger to ignore line after ands for ascii, not binary | Eddie Hung | 2019-02-17 | 1 | -2/+1 | |
| | | | | | | * | | | | | | One more merge conflict | Eddie Hung | 2019-02-17 | 1 | -6/+1 | |
| | | | | | | * | | | | | | Merge branch 'dff_init' into read_aiger | Eddie Hung | 2019-02-17 | 0 | -0/+0 | |
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| | * | | | | | | | | | | | Merge https://github.com/YosysHQ/yosys into dff_init | Eddie Hung | 2019-02-17 | 9 | -100/+345 | |
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| | | | | | | * | | | | | | Merge https://github.com/YosysHQ/yosys into read_aiger | Eddie Hung | 2019-02-17 | 9 | -100/+349 | |
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| * | | | | | | | | | | | | Merge pull request #811 from ucb-bar/firrtlfixes | Clifford Wolf | 2019-02-17 | 6 | -56/+298 | |
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| | * | | | | | | | | | | | Removed unused variables, functions. | Jim Lawson | 2019-02-15 | 1 | -20/+0 | |
| | * | | | | | | | | | | | Append (instead of over-writing) EXTRA_FLAGS | Jim Lawson | 2019-02-15 | 1 | -1/+1 | |
| | * | | | | | | | | | | | Update cells supported for verilog to FIRRTL conversion. | Jim Lawson | 2019-02-15 | 5 | -55/+317 | |
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| * | | | | | | | | | | | Fix sign handling of real constants | Clifford Wolf | 2019-02-13 | 1 | -5/+4 | |
| * | | | | | | | | | | | Merge pull request #802 from whitequark/write_verilog_async_mem_ports | Clifford Wolf | 2019-02-12 | 1 | -38/+41 | |
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| | * | | | | | | | | | | | write_verilog: correctly emit asynchronous transparent ports. | whitequark | 2019-01-29 | 1 | -38/+41 | |
| * | | | | | | | | | | | | Merge pull request #806 from daveshah1/fsm_opt_no_reset | Clifford Wolf | 2019-02-12 | 1 | -1/+2 | |
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| | * | | | | | | | | | | | fsm_opt: Fix runtime error for FSMs without a reset state | David Shah | 2019-02-07 | 1 | -1/+2 | |
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| | | | | | * | | | | | | Missing headers for Xcode? | Eddie Hung | 2019-02-12 | 1 | -0/+2 | |
| | | | | | * | | | | | | Merge branch 'read_aiger' of github.com:eddiehung/yosys into read_aiger | Eddie Hung | 2019-02-12 | 1 | -3/+1 | |
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| | | | | | | * | | | | | | Do not break for constraints | Eddie Hung | 2019-02-11 | 1 | -1/+0 | |
| | | | | | | * | | | | | | No increment line_count for binary ANDs | Eddie Hung | 2019-02-11 | 1 | -1/+1 | |
| | | | | | | * | | | | | | Do not ignore newline after AND in binary AIG | Eddie Hung | 2019-02-11 | 1 | -1/+0 | |
| | | | | | * | | | | | | | Use module->add{Not,And}Gate() functions | Eddie Hung | 2019-02-12 | 1 | -8/+2 | |
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| | | | | | * | | | | | | Merge remote-tracking branch 'origin/dff_init' into read_aiger | Eddie Hung | 2019-02-08 | 2 | -7/+7 | |
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| | | * | | | | | | | | | Cope WIDTH of ff/latch cells is default of zero | Eddie Hung | 2019-02-06 | 1 | -6/+6 | |
| | | * | | | | | | | | | Remove check for cell->name[0] == '$' | Eddie Hung | 2019-02-06 | 1 | -1/+1 | |
| | | | | | * | | | | | | addDff -> addDffGate as per @daveshah1 | Eddie Hung | 2019-02-08 | 1 | -1/+1 | |
| | | | | | * | | | | | | Fix tabulation | Eddie Hung | 2019-02-08 | 1 | -28/+28 | |
| | | | | | * | | | | | | -module_name arg to go before -clk_name | Eddie Hung | 2019-02-08 | 1 | -7/+7 | |
| | | | | | * | | | | | | Support and differentiate between ASCII and binary AIG testing | Eddie Hung | 2019-02-08 | 2 | -2/+6 | |
| | | | | | * | | | | | | Add missing "[options]" to read_blif help | Eddie Hung | 2019-02-08 | 1 | -1/+1 | |
| | | | | | * | | | | | | Allow module name to be determined by argument too | Eddie Hung | 2019-02-08 | 2 | -14/+44 | |
| | | | | | * | | | | | | Refactor into AigerReader class | Eddie Hung | 2019-02-08 | 2 | -79/+92 | |
| | | | | | * | | | | | | Parse binary AIG files | Eddie Hung | 2019-02-08 | 1 | -49/+164 | |
| | | | | | * | | | | | | Add binary AIGs converted from AAG | Eddie Hung | 2019-02-08 | 14 | -0/+51 | |
| | | | | | * | | | | | | Refactor to parse_aiger_header() | Eddie Hung | 2019-02-08 | 1 | -26/+32 | |
| | | | | | * | | | | | | Add comment | Eddie Hung | 2019-02-08 | 1 | -0/+1 | |
| | | | | | * | | | | | | Handle reset logic in latches | Eddie Hung | 2019-02-08 | 1 | -2/+17 | |
| | | | | | * | | | | | | Change literal vars from int to unsigned | Eddie Hung | 2019-02-08 | 1 | -1/+1 | |
| | | | | | * | | | | | | Create clk outside of latch loop | Eddie Hung | 2019-02-08 | 1 | -7/+9 | |
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index : iCE40/yosys | |
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