| Commit message (Expand) | Author | Age | Files | Lines | ||
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| | * | | ecp5: Sim model fixes | David Shah | 2018-10-19 | 1 | -3/+5 | |
| | * | | ecp5: Add latch inference | David Shah | 2018-10-19 | 3 | -3/+12 | |
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| * | | Merge pull request #672 from daveshah1/fix_bram | Clifford Wolf | 2018-10-19 | 1 | -0/+1 | |
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| | * | | memory_bram: Reset make_outreg when growing read ports | David Shah | 2018-10-19 | 1 | -0/+1 | |
| * | | | Merge pull request #671 from rafaeltp/master | Clifford Wolf | 2018-10-19 | 1 | -2/+3 | |
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| | * | | adding offset info to memories | rafaeltp | 2018-10-18 | 1 | -1/+1 | |
| | * | | adding offset info to memories | rafaeltp | 2018-10-18 | 1 | -2/+3 | |
| * | | | Merge pull request #670 from rubund/feature/basic_svinterface_test | Clifford Wolf | 2018-10-19 | 6 | -9/+248 | |
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| | * | | Basic test for checking correct synthesis of SystemVerilog interfaces | Ruben Undheim | 2018-10-18 | 6 | -9/+248 | |
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| * | | Update ABC to git rev 14d985a | Clifford Wolf | 2018-10-18 | 1 | -1/+1 | |
| * | | Merge pull request #659 from rubund/sv_interfaces | Clifford Wolf | 2018-10-18 | 11 | -21/+649 | |
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| | * | | Handle FIXME for modport members without type directly in front | Ruben Undheim | 2018-10-13 | 1 | -6/+8 | |
| | * | | Documentation improvements etc. | Ruben Undheim | 2018-10-13 | 5 | -38/+77 | |
| | * | | Fix build error with clang | Ruben Undheim | 2018-10-12 | 1 | -1/+1 | |
| | * | | Support for 'modports' for System Verilog interfaces | Ruben Undheim | 2018-10-12 | 8 | -14/+121 | |
| | * | | Synthesis support for SystemVerilog interfaces | Ruben Undheim | 2018-10-12 | 10 | -21/+501 | |
| * | | | Merge pull request #657 from mithro/xilinx-vpr | Clifford Wolf | 2018-10-18 | 1 | -3/+2 | |
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| | * | | | xilinx: Still map LUT7/LUT8 to Xilinx specific primitives. | Tim 'mithro' Ansell | 2018-10-08 | 1 | -3/+2 | |
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| * | | | Merge pull request #664 from tklam/ignore-verilog-protect | Clifford Wolf | 2018-10-18 | 1 | -0/+3 | |
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| | * | | | ignore protect endprotect | argama | 2018-10-16 | 1 | -0/+3 | |
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| * | | | Update ABC to git rev c5b48bb | Clifford Wolf | 2018-10-17 | 1 | -1/+1 | |
| * | | | Minor code cleanups in liberty front-end | Clifford Wolf | 2018-10-17 | 1 | -16/+5 | |
| * | | | Merge pull request #660 from tklam/parse-liberty-detect-ff-latch | Clifford Wolf | 2018-10-17 | 1 | -0/+17 | |
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| | * | | | detect ff/latch before processing other nodes | argama | 2018-10-14 | 1 | -0/+17 | |
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| * | | | Merge pull request #663 from aman-goel/master | Clifford Wolf | 2018-10-17 | 1 | -32/+51 | |
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| | * | | | Minor update | Aman Goel | 2018-10-15 | 2 | -3/+3 | |
| | * | | | Update to .smv backend | Aman Goel | 2018-10-01 | 2 | -35/+54 | |
| | * | | | Merge pull request #4 from YosysHQ/master | Aman Goel | 2018-10-01 | 31 | -107/+529 | |
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| * | \ \ \ | Merge pull request #658 from daveshah1/ecp5_bram | Clifford Wolf | 2018-10-17 | 9 | -20/+371 | |
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| | * | | | | | ecp5: Disable LSR inversion | David Shah | 2018-10-16 | 2 | -21/+21 | |
| | * | | | | | BRAM improvements | David Shah | 2018-10-12 | 1 | -11/+16 | |
| | * | | | | | ecp5: Adding BRAM maps for all size options | David Shah | 2018-10-10 | 1 | -1/+64 | |
| | * | | | | | ecp5: First BRAM type maps successfully | David Shah | 2018-10-10 | 8 | -10/+76 | |
| | * | | | | | ecp5: Script for BRAM IO connections | David Shah | 2018-10-10 | 4 | -64/+115 | |
| | * | | | | | ecp5: Adding BRAM initialisation and config | David Shah | 2018-10-09 | 5 | -0/+73 | |
| | * | | | | | ecp5: Add blackbox for DP16KD | David Shah | 2018-10-05 | 1 | -0/+93 | |
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| * | | | | | Merge pull request #641 from tklam/master | Clifford Wolf | 2018-10-17 | 1 | -0/+69 | |
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| | * | | | | | stop check_signal_in_fanout from traversing FFs | tklam | 2018-10-13 | 1 | -2/+2 | |
| | * | | | | | stop check_signal_in_fanout from traversing FFs | tklam | 2018-10-13 | 1 | -1/+12 | |
| | * | | | | | Merge branch 'master' of https://github.com/YosysHQ/yosys | tklam | 2018-10-13 | 6 | -17/+61 | |
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| | * | | | | | Merge branch 'master' of https://github.com/YosysHQ/yosys | tklam | 2018-10-03 | 4 | -7/+12 | |
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| | * | | | | | | fix bug: pass by reference | tklam | 2018-09-26 | 1 | -1/+1 | |
| | * | | | | | | Fix issue #639 | TK Lam | 2018-09-26 | 1 | -0/+58 | |
| * | | | | | | | Merge pull request #638 from udif/pr_reg_wire_error | Clifford Wolf | 2018-10-17 | 1 | -0/+12 | |
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| | * | | | | | | | Fixed issue #630 by fixing a minor typo in the previous commit | Udi Finkelstein | 2018-09-25 | 1 | -2/+2 | |
| | * | | | | | | | Merge branch 'master' into pr_reg_wire_error | Udi Finkelstein | 2018-09-18 | 226 | -1397/+5434 | |
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| | * | | | | | | | | Fixed remaining cases where we check fo wire reg/wire incorrect assignments | Udi Finkelstein | 2018-09-18 | 1 | -0/+12 | |
| * | | | | | | | | | We have 2018 now | Clifford Wolf | 2018-10-16 | 2 | -2/+2 | |
| * | | | | | | | | | After release is before release | Clifford Wolf | 2018-10-16 | 2 | -1/+9 | |
| * | | | | | | | | | Merge branch 'yosys-0.8-rc' | Clifford Wolf | 2018-10-16 | 2 | -141/+1201 | |
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