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* Add firrtl backend support for generic parameters in blackbox componentsSahand Kashani2020-07-231-58/+222
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previous blackbox components were just emitted with their interface ports, but their generic parameters were never emitted and it was therefore impossible to customize them. This commit adds support for blackbox generic parameters, though support is only provided for INTEGER and STRING parameters. Other types of parameters such as DOUBLEs, ..., would result in undefined behavior here. This allows the emission of custom extmodule instances such as the following: extmodule fourteennm_lcell_comb_<instName>: input cin: UInt<1> output combout: UInt<1> output cout: UInt<1> input dataa: UInt<1> input datab: UInt<1> input datac: UInt<1> input datad: UInt<1> input datae: UInt<1> input dataf: UInt<1> input datag: UInt<1> input datah: UInt<1> input sharein: UInt<1> output shareout: UInt<1> output sumout: UInt<1> defname = fourteennm_lcell_comb parameter extended_lut = "off" parameter lut_mask = "b0001001000010010000100100001001000010010000100100001001000010010" parameter shared_arith = "off"
* Merge pull request #2215 from boqwxp/qbfsat-solver-optionsclairexen2020-07-214-4/+45
|\ | | | | qbfsat, smt2, smtio: Add `-solver-option` to allow specifying SMT-LIBv2 `(set-option ...)` commands
| * smtio: Emit `mode: start` options before `set-logic` command and any other ↵Alberto Gonzalez2020-07-201-1/+8
| | | | | | | | | | | | options after it. Refer to the SMT-LIB specification, section 4.1.7. According to the spec, some options can only be specified in `start` mode. Once the solver sees `set-logic`, it moves to `assert` mode.
| * smtio: Add support for parsing `yosys-smt2-solver-option` info statements.Alberto Gonzalez2020-07-201-3/+10
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| * qbfsat: Add `-solver-option` option.Alberto Gonzalez2020-07-202-1/+15
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| * smt2: Add `-solver-option` option.Alberto Gonzalez2020-07-201-0/+13
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* Merge pull request #2282 from YosysHQ/claire/satunsatclairexen2020-07-202-4/+4
|\ | | | | Only allow "sat" and "unsat" smt solver responses in yosys-smtbmc
| * Only allow "sat" and "unsat" smt solver responses in yosys-smtbmcClaire Wolf2020-07-202-4/+4
| | | | | | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
* | celltypes: Fix EN port name for some FF types.Marcelina Kościelnicka2020-07-201-4/+4
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* Merge pull request #2276 from YosysHQ/mwk/satgen-ccclairexen2020-07-203-1166/+1190
|\ | | | | satgen: Move importCell out of the header.
| * satgen: Move importCell out of the header.Marcelina Kościelnicka2020-07-193-1166/+1190
|/ | | | | This function has no hope of ever getting inlined anyway, and it speeds up yosys compile time by 7%.
* Merge pull request #2275 from YosysHQ/mwk/sf2-clkint-fixMiodrag Milanović2020-07-171-2/+6
|\ | | | | sf2: Emit CLKINT even if -clkbuf not passed
| * sf2: Emit CLKINT even if -clkbuf not passedMarcelina Kościelnicka2020-07-171-2/+6
|/ | | | This restores pre #2229 behavior.
* Merge pull request #2274 from YosysHQ/mwk/anlogic-ff-fixMiodrag Milanović2020-07-171-12/+12
|\ | | | | anlogic: Fix FF mapping.
| * anlogic: Fix FF mapping.Marcelina Kościelnicka2020-07-171-12/+12
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* | Merge pull request #2229 from Ravenslofty/sf2_remove_sf2_iobsclairexen2020-07-164-214/+135
|\ \ | | | | | | sf2: replace sf2_iobs with {clkbuf,iopad}map
| * | sf2: replace sf2_iobs with {clkbuf,iopad}mapDan Ravensloft2020-07-094-214/+135
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* | | Merge pull request #2273 from whitequark/write-verilog-always-star-initialclairexen2020-07-161-0/+5
|\ \ \ | |_|/ |/| | verilog_backend: in non-SV mode, add a trigger for `always @*`
| * | verilog_backend: in non-SV mode, add a trigger for `always @*`.whitequark2020-07-161-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit only affects translation of RTLIL processes (for which there is limited support). Due to the event-driven nature of Verilog, processes like reg x; always @* x <= 1; may never execute. This can be fixed in SystemVerilog code by using `always_comb` instead of `always @*`, but in Verilog-2001 the options are limited. This commit implements the following workaround: reg init = 0; reg x; always @* begin if (init) begin end x <= 1; end Fixes #2271.
* | | Merge pull request #2272 from whitequark/write-verilog-svclairexen2020-07-162-11/+20
|\| | | | | | | | verilog_backend: add `-sv` option, make `-o <filename>.sv` work
| * | verilog_backend: add `-sv` option, make `-o <filename>.sv` work.whitequark2020-07-162-11/+20
| | | | | | | | | | | | See #2271.
* | | Merge pull request #2238 from YosysHQ/mwk/dfflegalize-anlogicMiodrag Milanović2020-07-164-62/+49
|\ \ \ | | | | | | | | anlogic: Use dfflegalize.
| * | | anlogic: Use dfflegalize.Marcelina Kościelnicka2020-07-144-62/+49
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* | | | Merge pull request #2226 from YosysHQ/mwk/nuke-efinix-gbufMiodrag Milanović2020-07-165-122/+11
|\ \ \ \ | | | | | | | | | | efinix: Nuke efinix_gbuf in favor of clkbufmap.
| * | | | efinix: Nuke efinix_gbuf in favor of clkbufmap.Marcelina Kościelnicka2020-07-045-122/+11
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* | | | | Merge pull request #2270 from whitequark/cxxrtl-fix-typowhitequark2020-07-161-1/+1
|\ \ \ \ \ | | | | | | | | | | | | cxxrtl: fix typo
| * | | | | cxxrtl: fix typo. NFC.whitequark2020-07-141-1/+1
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* | | | | Merge pull request #2269 from YosysHQ/claire/bisonwallwhitequark2020-07-152-64/+57
|\ \ \ \ \ | | | | | | | | | | | | Use "bison -Wall -Werror" for verilog front-end
| * | | | | Treat all bison warnings as errors in verilog front-endClaire Wolf2020-07-151-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
| * | | | | Use %precedence in verilog_parser.yClaire Wolf2020-07-151-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
| * | | | | Fix bison warnings for missing %emptyClaire Wolf2020-07-151-59/+52
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
| * | | | | Run bison with -Wall for verilog front-endClaire Wolf2020-07-151-1/+1
|/ / / / / | | | | | | | | | | | | | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
* | | | | Merge pull request #2257 from antmicro/fix-conflictsclairexen2020-07-155-9/+59
|\ \ \ \ \ | | | | | | | | | | | | Restore #2203 and #2244 and fix parser conflicts
| * | | | | Add missing semicolonsKamil Rakoczy2020-07-151-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
| * | | | | Fix S/R conflictsKamil Rakoczy2020-07-101-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit fixes S/R conflicts introduced by commit 6f9be93. Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
| * | | | | Fix R/R conflictsKamil Rakoczy2020-07-101-10/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit fixes R/R conflicts introduced by commit 7e83a51. Parameter logic is already defined as part of `param_range_type` rule. Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
| * | | | | Revert "Revert PRs #2203 and #2244."Kamil Rakoczy2020-07-105-10/+68
| | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 9c120b89ace6c111aa4677616947d18d980b9c1a.
* | | | | | opt_merge: Dedup one more use of FF cell type list.Marcelina Kościelnicka2020-07-151-3/+1
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* | | | | | achronix: Use dfflegalize.Marcelina Kościelnicka2020-07-141-1/+1
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* | | | | intel: Use dfflegalize.Marcelina Kościelnicka2020-07-138-178/+17
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* | | | | Revert "intel_alm: direct M10K instantiation"Lofty2020-07-138-128/+38
| | | | | | | | | | | | | | | | | | | | This reverts commit 09ecb9b2cf3ab76841d30712bf70dafc6d47ef67.
* | | | | Merge pull request #2263 from whitequark/cxxrtl-capi-eval-commitwhitequark2020-07-132-0/+20
|\ \ \ \ \ | | | | | | | | | | | | cxxrtl: expose eval() and commit() via the C API
| * | | | | cxxrtl: expose eval() and commit() via the C API.whitequark2020-07-122-0/+20
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* | | | | xilinx: Fix srl regression.Marcelina Kościelnicka2020-07-122-2/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Of standard yosys cells, xilinx_srl only works on $_DFF_?_ and $_DFFE_?P_, which get upgraded to $_SDFFE_?P?P_ by dfflegalize at the point where xilinx_srl is called for non-abc9. Fix this by running ff_map.v first, resulting in FDRE cells, which are handled correctly.
* | | | | proc_dlatch: Remove init values for combinatorial processes.Marcelina Kościelnicka2020-07-121-0/+33
| | | | | | | | | | | | | | | | | | | | Fixes #2258.
* | | | | dfflegalize: Gather init values from all wires.Marcelina Kościelnicka2020-07-121-1/+1
| | | | | | | | | | | | | | | | | | | | Skipping non-selected wires is unsound in an obvious way.
* | | | | Merge pull request #2256 from YosysHQ/claire/fix2241clairexen2020-07-101-0/+2
|\ \ \ \ \ | |/ / / / |/| | | | Add AST_EDGE support to AstNode::detect_latch()
| * | | | Add AST_EDGE support to AstNode::detect_latch(), fixes #2241Claire Wolf2020-07-101-0/+2
|/ / / / | | | | | | | | | | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
* | | | Merge pull request #2255 from whitequark/bison-Werror-conflictswhitequark2020-07-096-69/+11
|\ \ \ \ | | | | | | | | | | verilog_parser: turn S/R and R/R conflicts into hard errors
| * | | | verilog_parser: turn S/R and R/R conflicts into hard errors.whitequark2020-07-091-1/+1
| | | | | | | | | | | | | | | | | | | | Fixes #2253.
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