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* Use conservative stack size for SMT2 on MacOSArjen Roodselaar2018-11-041-1/+6
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* Add warning for SV "restrict" without "property"Clifford Wolf2018-11-041-2/+11
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add proper error message for when smtbmc "append" failsClifford Wolf2018-11-041-2/+10
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Various indenting fixes in AST front-end (mostly space vs tab issues)Clifford Wolf2018-11-043-99/+69
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge pull request #687 from trcwm/masterClifford Wolf2018-11-042-4/+10
|\ | | | | Liberty file: error when it contains pin references to non-existing pins
| * Liberty file newline handling is more relaxed. More descriptive error messageNiels Moseley2018-11-031-4/+7
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| * Report an error when a liberty file contains pin references that reference ↵Niels Moseley2018-11-031-0/+3
| | | | | | | | non-existing pins
* | Merge pull request #688 from ZipCPU/rosenfellClifford Wolf2018-11-041-2/+8
|\ \ | |/ |/| Make rose and fell dependent upon LSB only
| * Make and dependent upon LSB onlyZipCPU2018-11-031-2/+8
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* Do not generate "reg assigned in a continuous assignment" warnings for "rand ↵Clifford Wolf2018-11-011-2/+15
| | | | | | reg" Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add support for signed $shift/$shiftx in smt2 back-endClifford Wolf2018-11-011-1/+3
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge branch 'igloo2'Clifford Wolf2018-10-315-0/+377
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| * Fix sf2 LUT interfaceClifford Wolf2018-10-312-12/+12
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Basic SmartFusion2 and IGLOO2 synthesis supportClifford Wolf2018-10-315-0/+377
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Merge pull request #680 from jburgess777/fix-empty-string-back-assertClifford Wolf2018-10-301-1/+1
|\ \ | |/ |/| Avoid assert when label is an empty string
| * Avoid assert when label is an empty stringJon Burgess2018-10-281-1/+1
|/ | | | | | | | | | | | | | Calling back() on an empty string is not allowed and triggers an assert with recent gcc: $ cd manual/PRESENTATION_Intro $ ../../yosys counter.ys ... /usr/include/c++/8/bits/basic_string.h:1136: std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::reference std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::back() [with _CharT = char; _Traits = std::char_traits<char>; _Alloc = std::allocator<char>; std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::reference = char&]: Assertion '!empty()' failed. 802 if (label.back() == ':' && GetSize(label) > 1) (gdb) p label $1 = ""
* Merge pull request #678 from whentze/masterClifford Wolf2018-10-251-2/+2
|\ | | | | Fix unhandled std::out_of_range in run_frontend() due to integer underflow
| * fix unhandled std::out_of_range when calling yosys with 3-character argumentwhentze2018-10-221-2/+2
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* | Fix minor typo in error messageClifford Wolf2018-10-251-1/+1
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Merge pull request #679 from udif/pr_syntax_errorClifford Wolf2018-10-2514-14/+78
|\ \ | | | | | | More meaningful SystemVerilog/Verilog parser error messages
| * | Rename the generic "Syntax error" message from the Verilog/SystemVerilog ↵Udi Finkelstein2018-10-2514-14/+78
| | | | | | | | | | | | | | | | | | | | | parser into unique, meaningful info on the error. Also add 13 compilation examples that triggers each of these messages.
* | | Merge pull request #677 from daveshah1/ecp5_dspClifford Wolf2018-10-233-1/+97
|\ \ \ | |_|/ |/| | ecp5: Add blackboxes for MULT18X18D and ALU54B
| * | ecp5: Remove DSP parameters that don't workDavid Shah2018-10-221-21/+0
| | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
| * | ecp5: Add DSP blackboxesDavid Shah2018-10-213-1/+118
| |/ | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
* | Improve read_verilog range out of bounds warningClifford Wolf2018-10-201-6/+6
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Merge pull request #674 from rubund/feature/svinterface_at_topClifford Wolf2018-10-2011-70/+599
|\ \ | |/ |/| Support for SystemVerilog interfaces as ports in the top level module + test case
| * Refactor code to avoid code duplication + added commentsRuben Undheim2018-10-204-136/+113
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| * Support for SystemVerilog interfaces as a port in the top level module + ↵Ruben Undheim2018-10-209-10/+561
| | | | | | | | test case
| * Fixed memory leakRuben Undheim2018-10-201-0/+1
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* Merge pull request #673 from daveshah1/ecp5_improveClifford Wolf2018-10-194-6/+17
|\ | | | | Small ECP5 improvements
| * ecp5: Sim model fixesDavid Shah2018-10-191-3/+5
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * ecp5: Add latch inferenceDavid Shah2018-10-193-3/+12
|/ | | | Signed-off-by: David Shah <dave@ds0.me>
* Merge pull request #672 from daveshah1/fix_bramClifford Wolf2018-10-191-0/+1
|\ | | | | memory_bram: Reset make_outreg when growing read ports
| * memory_bram: Reset make_outreg when growing read portsDavid Shah2018-10-191-0/+1
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | Merge pull request #671 from rafaeltp/masterClifford Wolf2018-10-191-2/+3
|\ \ | | | | | | adding offset info to memories on verilog output
| * | adding offset info to memoriesrafaeltp2018-10-181-1/+1
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| * | adding offset info to memoriesrafaeltp2018-10-181-2/+3
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* | | Merge pull request #670 from rubund/feature/basic_svinterface_testClifford Wolf2018-10-196-9/+248
|\ \ \ | |/ / |/| | Basic test for checking correct synthesis of SystemVerilog interfaces
| * | Basic test for checking correct synthesis of SystemVerilog interfacesRuben Undheim2018-10-186-9/+248
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* | Update ABC to git rev 14d985aClifford Wolf2018-10-181-1/+1
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Merge pull request #659 from rubund/sv_interfacesClifford Wolf2018-10-1811-21/+649
|\ \ | | | | | | Support for SystemVerilog interfaces and modports
| * | Handle FIXME for modport members without type directly in frontRuben Undheim2018-10-131-6/+8
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| * | Documentation improvements etc.Ruben Undheim2018-10-135-38/+77
| | | | | | | | | | | | | | | | | | | | | | | | | | | - Mention new feature in the SystemVerilog section in the README file - Commented changes much better - Rename a few signals to make it clearer - Prevent warning for unused signals in an easier way - Add myself as copyright holder to 2 files - Fix one potential memory leak (delete 'wire' if not in modport)
| * | Fix build error with clangRuben Undheim2018-10-121-1/+1
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| * | Support for 'modports' for System Verilog interfacesRuben Undheim2018-10-128-14/+121
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| * | Synthesis support for SystemVerilog interfacesRuben Undheim2018-10-1210-21/+501
| | | | | | | | | | | | This time doing the changes mostly in AST before RTLIL generation
* | | Merge pull request #657 from mithro/xilinx-vprClifford Wolf2018-10-181-3/+2
|\ \ \ | | | | | | | | xilinx: Still map LUT7/LUT8 to Xilinx specific primitives when using `-vpr`
| * | | xilinx: Still map LUT7/LUT8 to Xilinx specific primitives.Tim 'mithro' Ansell2018-10-081-3/+2
| |/ / | | | | | | | | | | | | Then if targeting vpr map all the Xilinx specific LUTs back into generic Yosys LUTs.
* | | Merge pull request #664 from tklam/ignore-verilog-protectClifford Wolf2018-10-181-0/+3
|\ \ \ | | | | | | | | Ignore protect endprotect
| * | | ignore protect endprotectargama2018-10-161-0/+3
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