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* | Fixed Verilog parser fix and more similar improvementsClifford Wolf2016-03-151-18/+9
* | Use left-recursive rule for cell_port_list in Verilog parser.Andrew Becker2016-03-151-6/+10
* | Bugfix in write_verilog for RTLIL processesClifford Wolf2016-03-141-9/+20
* | Cleanups and improvements in examples/cmos/Clifford Wolf2016-03-115-12/+19
* | Merge commit 'b34385ec924b6067c1f82bdbae923f8062518956'Clifford Wolf2016-03-115-9/+76
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| * | Completed ngspice digital example with verilog tbUros Platise2016-03-055-9/+76
* | | Fixed typos in verilog_defaults help messageClifford Wolf2016-03-101-3/+3
* | | Added "write_edif -nogndvcc"Clifford Wolf2016-03-081-17/+34
* | | Added examples/cxx-api/evaldemo.ccClifford Wolf2016-03-081-0/+55
* | | Merge branch 'master' of github.com:cliffordwolf/yosysClifford Wolf2016-03-077-25/+123
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| * | Added digital (xspice) example code to examples/cmos/Clifford Wolf2016-03-024-1/+70
| * | Be more conservative with net names in spice outputClifford Wolf2016-03-021-18/+47
| * | Merge pull request #119 from SebKuzminsky/spelling-fixesClifford Wolf2016-02-292-6/+6
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| | * | user-facing spelling fixesSebastian Kuzminsky2016-02-282-6/+6
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* / / Using "mfs" and "lutpack" in ABC lut mappingClifford Wolf2016-03-071-5/+14
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* | We are now in 0.6+ developmentClifford Wolf2016-02-261-1/+1
* | Yosys 0.6Clifford Wolf2016-02-261-1/+1
* | Fixed BLIF parser for empty port assignmentsClifford Wolf2016-02-241-2/+2
* | Use easyer-to-read unoptimized ceil_log2()Clifford Wolf2016-02-151-18/+5
* | Updated ABC to ae7d65e71adcClifford Wolf2016-02-151-1/+1
* | Updated command reference in manualClifford Wolf2016-02-143-16/+364
* | Changelog for upcoming 0.6 releaseClifford Wolf2016-02-141-0/+88
* | Fixed more visual studio warningsClifford Wolf2016-02-141-5/+3
* | Fixed some visual studio warningsClifford Wolf2016-02-138-10/+10
* | Merge branch 'master' of github.com:cliffordwolf/yosysClifford Wolf2016-02-131-1/+1
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| * | Fixed MXE ABC buildClifford Wolf2016-02-131-1/+1
* | | Added "int ceil_log2(int)" functionClifford Wolf2016-02-135-10/+58
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* | Run dffsr2dff in synth_xilinxClifford Wolf2016-02-131-0/+2
* | Support for more Verific primitives (patch I got per email)Clifford Wolf2016-02-131-1/+31
* | Updated ABCClifford Wolf2016-02-081-1/+1
* | Work around DDR dout sim glitches in ice40 SB_IO sim modelClifford Wolf2016-02-071-1/+7
* | Updated ABCClifford Wolf2016-02-071-1/+1
* | Added "stat -liberty" for calculating chip areaClifford Wolf2016-02-041-6/+60
* | Bugfix in Verific front-endClifford Wolf2016-02-031-2/+5
* | Updated verific build instructionsClifford Wolf2016-02-021-2/+0
* | Improved dffsr2dff passClifford Wolf2016-02-021-5/+50
* | Added dffsr2dffClifford Wolf2016-02-023-0/+171
* | Added addBufGate module methodClifford Wolf2016-02-023-0/+8
* | Use alphanumerical order instead of idstring idx in opt_clean compare_signals()Clifford Wolf2016-02-021-1/+1
* | Added CodeOfConductClifford Wolf2016-02-011-0/+73
* | Updated ABC to hg rev ee212a9e94dfClifford Wolf2016-02-011-1/+1
* | Progress in cell library documentationClifford Wolf2016-02-011-0/+238
* | Added "abc -luts" option, Improved Xilinx logic mappingClifford Wolf2016-02-012-15/+39
* | Improvements in dfflibmap (FFs with Q/QN outputs, DFFs from ADFFs)Clifford Wolf2016-02-011-8/+68
* | SigMap performance improvementClifford Wolf2016-02-011-1/+7
* | hashlib mfp<> performance improvementsClifford Wolf2016-02-011-2/+7
* | Added reserve() method to haslib classes andClifford Wolf2016-01-311-2/+6
* | Merge branch 'rtlil_remove2_speedup' of https://github.com/kc8apf/yosysClifford Wolf2016-01-312-14/+88
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| * | rtlil: Improve performance of SigSpec::extract(SigSpec, SigSpec*)Rick Altherr2016-01-311-2/+31
| * | rtlil: speed up SigSpec::sort_and_unify()Rick Altherr2016-01-311-1/+11
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