| Commit message (Expand) | Author | Age | Files | Lines | ||
|---|---|---|---|---|---|---|
| ... | ||||||
| | * | | | | | Progress in pmgen | Clifford Wolf | 2019-01-15 | 1 | -3/+11 | |
| | * | | | | | Progress in pmgen, add pmgen README | Clifford Wolf | 2019-01-15 | 3 | -14/+260 | |
| | * | | | | | Fix pmgen "reject" statement | Clifford Wolf | 2019-01-15 | 1 | -1/+1 | |
| | * | | | | | Progress in pmgen | Clifford Wolf | 2019-01-15 | 3 | -36/+139 | |
| | * | | | | | Progress in pmgen | Clifford Wolf | 2019-01-15 | 3 | -21/+157 | |
| | * | | | | | Progress in pmgen | Clifford Wolf | 2019-01-15 | 5 | -8/+347 | |
| | * | | | | | Add mockup .pmg (pattern matcher generator) file | Clifford Wolf | 2019-01-15 | 1 | -0/+75 | |
| * | | | | | | Merge pull request #821 from eddiehung/dff_init | Clifford Wolf | 2019-02-21 | 1 | -4/+2 | |
| |\ \ \ \ \ \ | |_|_|/ / / |/| | | | | | ||||||
| | * | | | | | Revert "Add -B option to autotest.sh to append to backend_opts" | Eddie Hung | 2019-02-21 | 1 | -4/+2 | |
| * | | | | | | Merge pull request #817 from eddiehung/dff_init | Eddie Hung | 2019-02-20 | 1 | -21/+0 | |
| |\| | | | | | ||||||
| | * | | | | | Remove simple_defparam tests | Eddie Hung | 2019-02-20 | 1 | -21/+0 | |
| * | | | | | | Merge pull request #805 from eddiehung/dff_init | Eddie Hung | 2019-02-19 | 4 | -2/+76 | |
| |\| | | | | | |_|/ / / |/| | | | | ||||||
| | * | | | | Instead of INIT param on cells, use initial statement with hier ref as | Eddie Hung | 2019-02-17 | 1 | -18/+13 | |
| | * | | | | Revert "Add INIT parameter to all ff/latch cells" | Eddie Hung | 2019-02-17 | 2 | -86/+43 | |
| | * | | | | Merge https://github.com/YosysHQ/yosys into dff_init | Eddie Hung | 2019-02-17 | 9 | -100/+345 | |
| | |\ \ \ \ | |/ / / / |/| | | | | ||||||
| * | | | | | Merge pull request #811 from ucb-bar/firrtlfixes | Clifford Wolf | 2019-02-17 | 6 | -56/+298 | |
| |\ \ \ \ \ | |_|_|_|/ |/| | | | | ||||||
| | * | | | | Removed unused variables, functions. | Jim Lawson | 2019-02-15 | 1 | -20/+0 | |
| | * | | | | Append (instead of over-writing) EXTRA_FLAGS | Jim Lawson | 2019-02-15 | 1 | -1/+1 | |
| | * | | | | Update cells supported for verilog to FIRRTL conversion. | Jim Lawson | 2019-02-15 | 5 | -55/+317 | |
| |/ / / / | ||||||
| * | | | | Fix sign handling of real constants | Clifford Wolf | 2019-02-13 | 1 | -5/+4 | |
| * | | | | Merge pull request #802 from whitequark/write_verilog_async_mem_ports | Clifford Wolf | 2019-02-12 | 1 | -38/+41 | |
| |\ \ \ \ | ||||||
| | * | | | | write_verilog: correctly emit asynchronous transparent ports. | whitequark | 2019-01-29 | 1 | -38/+41 | |
| * | | | | | Merge pull request #806 from daveshah1/fsm_opt_no_reset | Clifford Wolf | 2019-02-12 | 1 | -1/+2 | |
| |\ \ \ \ \ | |_|_|_|/ |/| | | | | ||||||
| | * | | | | fsm_opt: Fix runtime error for FSMs without a reset state | David Shah | 2019-02-07 | 1 | -1/+2 | |
| |/ / / / | ||||||
| | | * | | Cope WIDTH of ff/latch cells is default of zero | Eddie Hung | 2019-02-06 | 1 | -6/+6 | |
| | | * | | Remove check for cell->name[0] == '$' | Eddie Hung | 2019-02-06 | 1 | -1/+1 | |
| | | * | | Refactor | Eddie Hung | 2019-02-06 | 1 | -21/+5 | |
| | | * | | write_verilog to cope with init attr on q when -noexpr | Eddie Hung | 2019-02-06 | 1 | -2/+32 | |
| | | * | | Add INIT parameter to all ff/latch cells | Eddie Hung | 2019-02-06 | 2 | -43/+86 | |
| | | * | | Add tests for simple cases using defparam | Eddie Hung | 2019-02-06 | 1 | -0/+21 | |
| | | * | | Add -B option to autotest.sh to append to backend_opts | Eddie Hung | 2019-02-06 | 1 | -2/+4 | |
| | | * | | Extend testcase | Eddie Hung | 2019-02-06 | 1 | -2/+34 | |
| | | * | | Add testcase | Eddie Hung | 2019-02-06 | 1 | -0/+10 | |
| | |/ / |/| | | ||||||
| * | | | Add missing blackslash-to-slash convertion to smtio.py (matching Smt2Worker::... | Clifford Wolf | 2019-02-06 | 1 | -1/+1 | |
| |/ / | ||||||
| * | | Merge pull request #798 from mmicko/master | Clifford Wolf | 2019-01-27 | 1 | -1/+1 | |
| |\ \ | ||||||
| | * | | Fixed Anlogic simulation model | Miodrag Milanovic | 2019-01-25 | 1 | -1/+1 | |
| * | | | Merge pull request #800 from whitequark/write_verilog_tribuf | Clifford Wolf | 2019-01-27 | 1 | -0/+12 | |
| |\ \ \ | ||||||
| | * | | | write_verilog: write $tribuf cell as ternary. | whitequark | 2019-01-27 | 1 | -0/+12 | |
| * | | | | Merge branch 'whitequark-write_verilog_keyword' | Clifford Wolf | 2019-01-27 | 5 | -69/+27 | |
| |\ \ \ \ | |/ / / |/| | | | ||||||
| | * | | | Remove asicworld tests for (unsupported) switch-level modelling | Clifford Wolf | 2019-01-27 | 4 | -69/+0 | |
| | * | | | write_verilog: escape names that match SystemVerilog keywords. | whitequark | 2019-01-27 | 1 | -0/+27 | |
| |/ / / | ||||||
| * | | | Merge pull request #796 from whitequark/proc_clean_typo | David Shah | 2019-01-25 | 1 | -1/+1 | |
| |\ \ \ | |/ / |/| | | ||||||
| | * | | proc_clean: fix critical typo. | whitequark | 2019-01-23 | 1 | -1/+1 | |
| |/ / | ||||||
| * | | Merge pull request #793 from whitequark/proc_clean_fix_fully_def | Clifford Wolf | 2019-01-19 | 1 | -1/+7 | |
| |\ \ | ||||||
| | * | | proc_clean: fix fully def check to consider compare/signal length. | whitequark | 2019-01-18 | 1 | -1/+7 | |
| |/ / | ||||||
| * | | Cleanups in igloo2 example design | Clifford Wolf | 2019-01-17 | 6 | -7/+4 | |
| * | | Add SF2 IO buffer insertion | Clifford Wolf | 2019-01-17 | 6 | -3/+171 | |
| * | | Improve Igloo2 example | Clifford Wolf | 2019-01-17 | 8 | -22/+41 | |
| * | | Add "synth_sf2 -vlog", fix "synth_sf2 -edif" | Clifford Wolf | 2019-01-17 | 1 | -2/+17 | |
| * | | Add "write_edif -gndvccy" | Clifford Wolf | 2019-01-17 | 1 | -5/+13 | |
| |/ | ||||||
 |
index : iCE40/yosys | |
| [no description] |
| aboutsummaryrefslogtreecommitdiffstats |